u-boot/drivers/ddr/imx/imx8ulp/Kconfig

menu "i.MX8ULP DDR controllers"
	depends on ARCH_IMX8ULP

config IMX8ULP_DRAM
	bool "imx8m dram"

config IMX8ULP_DRAM_PHY_PLL_BYPASS
	bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
	depends on IMX8ULP_DRAM

config SAVED_DRAM_TIMING_BASE
	hex "Define the base address for saved dram timing"
	help
	  The DRAM config timing data need to be saved into sram
	  for low power use.
	default 0x20055000

endmenu
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com> 2021-08-07 08:01:11 +00:00			`menu "i.MX8ULP DDR controllers"`
			`depends on ARCH_IMX8ULP`

			`config IMX8ULP_DRAM`
			`bool "imx8m dram"`

			`config IMX8ULP_DRAM_PHY_PLL_BYPASS`
			`bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "`
			`depends on IMX8ULP_DRAM`

imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-10-29 01:46:33 +00:00			`config SAVED_DRAM_TIMING_BASE`
			`hex "Define the base address for saved dram timing"`
			`help`
			`The DRAM config timing data need to be saved into sram`
			`for low power use.`
ddr: imx8ulp: Change DRAM timing save area to 0x20055000 To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> 2023-01-31 08:42:19 +00:00			`default 0x20055000`
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 2021-10-29 01:46:33 +00:00
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com> 2021-08-07 08:01:11 +00:00			`endmenu`