2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2002-11-03 00:38:21 +00:00
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/*
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* armboot - Startup Code for ARM920 CPU-core
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*
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2011-08-04 16:45:45 +00:00
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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2009-05-13 08:54:10 +00:00
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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2002-11-03 00:38:21 +00:00
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*/
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2010-10-26 12:34:52 +00:00
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#include <asm-offsets.h>
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2009-07-27 08:06:39 +00:00
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#include <common.h>
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2002-11-03 00:38:21 +00:00
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#include <config.h>
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/*
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*************************************************************************
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*
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2007-09-05 15:04:41 +00:00
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* Startup Code (called from the ARM reset exception vector)
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2002-11-03 00:38:21 +00:00
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*
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* do important init only if we don't start from memory!
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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2014-04-15 14:13:51 +00:00
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.globl reset
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2010-09-17 11:10:43 +00:00
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2014-04-15 14:13:51 +00:00
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reset:
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2002-11-03 00:38:21 +00:00
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/*
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* set the cpu to SVC32 mode
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*/
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2009-10-10 04:30:22 +00:00
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0xd3
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msr cpsr, r0
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2007-09-05 15:04:41 +00:00
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2021-05-22 12:47:07 +00:00
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#if defined(CONFIG_AT91RM9200DK)
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2007-08-14 09:10:52 +00:00
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/*
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2007-09-05 15:04:41 +00:00
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* relocate exception table
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2007-08-14 09:10:52 +00:00
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*/
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ldr r0, =_start
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ldr r1, =0x0
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mov r2, #16
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copyex:
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subs r2, r2, #1
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ldr r3, [r0], #4
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str r3, [r1], #4
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bne copyex
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#endif
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2002-11-03 00:38:21 +00:00
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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2005-04-04 12:44:11 +00:00
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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2002-11-03 00:38:21 +00:00
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bl cpu_init_crit
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#endif
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2013-01-08 10:18:02 +00:00
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bl _main
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2010-09-17 11:10:43 +00:00
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/*------------------------------------------------------------------------------*/
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2013-01-08 10:18:02 +00:00
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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mov pc, lr
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2002-11-03 00:38:21 +00:00
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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2006-04-03 13:46:10 +00:00
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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2002-11-03 00:38:21 +00:00
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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2016-02-25 01:23:34 +00:00
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orr r0, r0, #0x00000002 @ set bit 1 (A) Align
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2002-11-03 00:38:21 +00:00
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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2016-05-05 13:28:06 +00:00
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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2002-11-03 00:38:21 +00:00
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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2005-04-02 23:52:25 +00:00
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* find a lowlevel_init.S in your board directory.
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2002-11-03 00:38:21 +00:00
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*/
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mov ip, lr
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2007-08-14 09:10:52 +00:00
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2005-04-02 23:52:25 +00:00
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bl lowlevel_init
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2002-11-03 00:38:21 +00:00
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mov lr, ip
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2016-05-05 13:28:06 +00:00
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#endif
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2002-11-03 00:38:21 +00:00
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mov pc, lr
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2006-04-03 13:46:10 +00:00
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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