mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 15:12:04 +00:00
Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code
This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
kevin.morfitt@fearnside-systems.co.uk
Tom Rix
parent
cd85662b34
commit
d67cce2dda
7 changed files with 906 additions and 821 deletions
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@ -40,7 +40,7 @@
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void do_irq (struct pt_regs *pt_regs)
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{
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S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
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u_int32_t intpnd = irq->INTPND;
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struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
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u_int32_t intpnd = readl(&irq->INTPND);
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}
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@ -32,6 +32,8 @@
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#include <common.h>
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#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
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#include <asm/io.h>
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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@ -53,49 +55,51 @@
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static ulong get_PLLCLK(int pllreg)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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ulong r, m, p, s;
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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ulong r, m, p, s;
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if (pllreg == MPLL)
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r = clk_power->MPLLCON;
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else if (pllreg == UPLL)
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r = clk_power->UPLLCON;
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else
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hang();
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if (pllreg == MPLL)
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r = readl(&clk_power->MPLLCON);
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else if (pllreg == UPLL)
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r = readl(&clk_power->UPLLCON);
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else
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hang();
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m = ((r & 0xFF000) >> 12) + 8;
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p = ((r & 0x003F0) >> 4) + 2;
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s = r & 0x3;
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m = ((r & 0xFF000) >> 12) + 8;
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p = ((r & 0x003F0) >> 4) + 2;
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s = r & 0x3;
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return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
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return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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return(get_PLLCLK(MPLL));
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return get_PLLCLK(MPLL);
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
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return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
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return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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return(get_PLLCLK(UPLL));
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return get_PLLCLK(UPLL);
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}
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#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
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#endif /* defined(CONFIG_S3C2400) ||
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defined (CONFIG_S3C2410) ||
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defined (CONFIG_TRAB) */
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@ -30,7 +30,11 @@
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*/
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#include <common.h>
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#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
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#if defined(CONFIG_S3C2400) || \
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defined(CONFIG_S3C2410) || \
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defined(CONFIG_TRAB)
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#include <asm/io.h>
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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@ -44,37 +48,40 @@ static ulong timer_clk;
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/* macro to read the 16 bit timer */
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static inline ulong READ_TIMER(void)
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{
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S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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return (timers->TCNTO4 & 0xffff);
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return readl(&timers->TCNTO4) & 0xffff;
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}
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static ulong timestamp;
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static ulong lastdec;
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int timer_init (void)
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int timer_init(void)
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{
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S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
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struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
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ulong tmr;
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/* use PWM Timer 4 because it has no output */
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/* prescaler for Timer 4 is 16 */
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timers->TCFG0 = 0x0f00;
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if (timer_load_val == 0)
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{
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writel(0x0f00, &timers->TCFG0);
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if (timer_load_val == 0) {
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/*
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* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
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* (default) and prescaler = 16. Should be 10390
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* @33.25MHz and 15625 @ 50 MHz
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*/
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timer_load_val = get_PCLK()/(2 * 16 * 100);
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timer_load_val = get_PCLK() / (2 * 16 * 100);
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timer_clk = get_PCLK() / (2 * 16);
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}
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/* load value for 10 ms timeout */
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lastdec = timers->TCNTB4 = timer_load_val;
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lastdec = timer_load_val;
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writel(timer_load_val, &timers->TCNTB4);
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/* auto load, manual update of Timer 4 */
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timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
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tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
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writel(tmr, &timers->TCON);
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/* auto load, start Timer 4 */
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timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
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tmr = (tmr & ~0x0700000) | 0x0500000;
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writel(tmr, &timers->TCON);
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timestamp = 0;
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return (0);
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@ -84,22 +91,22 @@ int timer_init (void)
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* timer without interrupts
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*/
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void reset_timer (void)
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void reset_timer(void)
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{
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reset_timer_masked ();
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reset_timer_masked();
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}
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ulong get_timer (ulong base)
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ulong get_timer(ulong base)
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{
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return get_timer_masked () - base;
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return get_timer_masked() - base;
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}
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void set_timer (ulong t)
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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void udelay (unsigned long usec)
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void udelay(unsigned long usec)
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{
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ulong tmo;
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ulong start = get_ticks();
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@ -112,21 +119,21 @@ void udelay (unsigned long usec)
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/*NOP*/;
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}
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void reset_timer_masked (void)
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void reset_timer_masked(void)
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{
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/* reset time */
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lastdec = READ_TIMER();
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timestamp = 0;
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}
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ulong get_timer_masked (void)
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ulong get_timer_masked(void)
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{
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ulong tmr = get_ticks();
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return tmr / (timer_clk / CONFIG_SYS_HZ);
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}
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void udelay_masked (unsigned long usec)
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void udelay_masked(unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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@ -138,7 +145,7 @@ void udelay_masked (unsigned long usec)
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tmo /= 1000;
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} else {
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tmo = usec * (timer_load_val * 100);
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tmo /= (1000*1000);
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tmo /= (1000 * 1000);
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}
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endtime = get_ticks() + tmo;
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@ -173,7 +180,7 @@ unsigned long long get_ticks(void)
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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ulong get_tbclk(void)
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{
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ulong tbclk;
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@ -193,30 +200,31 @@ ulong get_tbclk (void)
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/*
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* reset the cpu by setting up the watchdog timer and let him time out
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*/
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void reset_cpu (ulong ignored)
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void reset_cpu(ulong ignored)
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{
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volatile S3C24X0_WATCHDOG * watchdog;
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struct s3c24x0_watchdog *watchdog;
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#ifdef CONFIG_TRAB
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extern void disable_vfd (void);
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disable_vfd();
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#endif
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watchdog = S3C24X0_GetBase_WATCHDOG();
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watchdog = s3c24x0_get_base_watchdog();
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/* Disable watchdog */
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watchdog->WTCON = 0x0000;
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writel(0x0000, &watchdog->WTCON);
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/* Initialize watchdog timer count register */
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watchdog->WTCNT = 0x0001;
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writel(0x0001, &watchdog->WTCNT);
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/* Enable watchdog timer; assert reset at timer timeout */
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watchdog->WTCON = 0x0021;
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writel(0x0021, &watchdog->WTCON);
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while(1); /* loop forever and wait for reset to happen */
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while (1)
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/* loop forever and wait for reset to happen */;
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/*NOTREACHED*/
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}
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#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
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#endif /* defined(CONFIG_S3C2400) ||
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defined (CONFIG_S3C2410) ||
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defined (CONFIG_TRAB) */
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@ -32,41 +32,43 @@
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# include <s3c2410.h>
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#endif
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int usb_cpu_init (void)
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{
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#include <asm/io.h>
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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int usb_cpu_init(void)
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{
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
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/*
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* Set the 48 MHz UPLL clocking. Values are taken from
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* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
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*/
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clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
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gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
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writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
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/* 1 = use pads related USB for USB host */
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writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
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/*
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* Enable USB host clock.
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*/
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clk_power->CLKCON |= (1 << 4);
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writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
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return 0;
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}
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int usb_cpu_stop (void)
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int usb_cpu_stop(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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/* may not want to do this */
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clk_power->CLKCON &= ~(1 << 4);
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writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
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return 0;
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}
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int usb_cpu_init_fail (void)
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int usb_cpu_init_fail(void)
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{
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S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
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clk_power->CLKCON &= ~(1 << 4);
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
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return 0;
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}
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# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
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# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
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#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
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File diff suppressed because it is too large
Load diff
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@ -11,22 +11,22 @@
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static int cc_to_error[16] = {
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/* mapping of the OHCI CC status to error codes */
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/* No Error */ 0,
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/* CRC Error */ USB_ST_CRC_ERR,
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/* Bit Stuff */ USB_ST_BIT_ERR,
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/* Data Togg */ USB_ST_CRC_ERR,
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/* Stall */ USB_ST_STALLED,
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/* DevNotResp */ -1,
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/* PIDCheck */ USB_ST_BIT_ERR,
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/* UnExpPID */ USB_ST_BIT_ERR,
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/* DataOver */ USB_ST_BUF_ERR,
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/* DataUnder */ USB_ST_BUF_ERR,
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/* reservd */ -1,
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/* reservd */ -1,
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/* BufferOver */ USB_ST_BUF_ERR,
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/* BuffUnder */ USB_ST_BUF_ERR,
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/* Not Access */ -1,
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/* Not Access */ -1
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/* No Error */ 0,
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/* CRC Error */ USB_ST_CRC_ERR,
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/* Bit Stuff */ USB_ST_BIT_ERR,
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/* Data Togg */ USB_ST_CRC_ERR,
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/* Stall */ USB_ST_STALLED,
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/* DevNotResp */ -1,
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/* PIDCheck */ USB_ST_BIT_ERR,
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/* UnExpPID */ USB_ST_BIT_ERR,
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/* DataOver */ USB_ST_BUF_ERR,
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/* DataUnder */ USB_ST_BUF_ERR,
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/* reservd */ -1,
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/* reservd */ -1,
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/* BufferOver */ USB_ST_BUF_ERR,
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/* BuffUnder */ USB_ST_BUF_ERR,
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/* Not Access */ -1,
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/* Not Access */ -1
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};
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/* ED States */
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@ -55,14 +55,13 @@ struct ed {
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struct usb_device *usb_dev;
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__u32 unused[3];
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} __attribute__((aligned(16)));
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typedef struct ed ed_t;
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} __attribute__ ((aligned(16)));
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/* TD info field */
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#define TD_CC 0xf0000000
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#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
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#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
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#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
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#define TD_CC_SET(td_p, cc) \
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{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
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#define TD_EC 0x0C000000
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#define TD_T 0x03000000
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#define TD_T_DATA0 0x02000000
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@ -112,8 +111,7 @@ struct td {
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__u32 data;
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__u32 unused2[2];
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} __attribute__((aligned(32)));
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typedef struct td td_t;
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} __attribute__ ((aligned(32)));
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#define OHCI_ED_SKIP (1 << 14)
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@ -123,15 +121,14 @@ typedef struct td td_t;
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* told the base address of. It must be 256-byte aligned.
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*/
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#define NUM_INTS 32 /* part of the OHCI standard */
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#define NUM_INTS 32 /* part of the OHCI standard */
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struct ohci_hcca {
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__u32 int_table[NUM_INTS]; /* Interrupt ED table */
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__u16 frame_no; /* current frame number */
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__u16 pad1; /* set to 0 on each frame_no change */
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__u32 done_head; /* info returned for an interrupt */
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u8 reserved_for_hc[116];
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} __attribute__((aligned(256)));
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__u32 int_table[NUM_INTS]; /* Interrupt ED table */
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__u16 frame_no; /* current frame number */
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__u16 pad1; /* set to 0 on each frame_no change */
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__u32 done_head; /* info returned for an interrupt */
|
||||
u8 reserved_for_hc[116];
|
||||
} __attribute__ ((aligned(256)));
|
||||
|
||||
/*
|
||||
* Maximum number of root hub ports.
|
||||
|
|
@ -145,35 +142,34 @@ struct ohci_hcca {
|
|||
*/
|
||||
struct ohci_regs {
|
||||
/* control and status registers */
|
||||
__u32 revision;
|
||||
__u32 control;
|
||||
__u32 cmdstatus;
|
||||
__u32 intrstatus;
|
||||
__u32 intrenable;
|
||||
__u32 intrdisable;
|
||||
__u32 revision;
|
||||
__u32 control;
|
||||
__u32 cmdstatus;
|
||||
__u32 intrstatus;
|
||||
__u32 intrenable;
|
||||
__u32 intrdisable;
|
||||
/* memory pointers */
|
||||
__u32 hcca;
|
||||
__u32 ed_periodcurrent;
|
||||
__u32 ed_controlhead;
|
||||
__u32 ed_controlcurrent;
|
||||
__u32 ed_bulkhead;
|
||||
__u32 ed_bulkcurrent;
|
||||
__u32 donehead;
|
||||
__u32 hcca;
|
||||
__u32 ed_periodcurrent;
|
||||
__u32 ed_controlhead;
|
||||
__u32 ed_controlcurrent;
|
||||
__u32 ed_bulkhead;
|
||||
__u32 ed_bulkcurrent;
|
||||
__u32 donehead;
|
||||
/* frame counters */
|
||||
__u32 fminterval;
|
||||
__u32 fmremaining;
|
||||
__u32 fmnumber;
|
||||
__u32 periodicstart;
|
||||
__u32 lsthresh;
|
||||
__u32 fminterval;
|
||||
__u32 fmremaining;
|
||||
__u32 fmnumber;
|
||||
__u32 periodicstart;
|
||||
__u32 lsthresh;
|
||||
/* Root hub ports */
|
||||
struct ohci_roothub_regs {
|
||||
__u32 a;
|
||||
__u32 b;
|
||||
__u32 status;
|
||||
__u32 portstatus[MAX_ROOT_PORTS];
|
||||
struct ohci_roothub_regs {
|
||||
__u32 a;
|
||||
__u32 b;
|
||||
__u32 status;
|
||||
__u32 portstatus[MAX_ROOT_PORTS];
|
||||
} roothub;
|
||||
} __attribute__((aligned(32)));
|
||||
|
||||
} __attribute__ ((aligned(32)));
|
||||
|
||||
/* OHCI CONTROL AND STATUS REGISTER MASKS */
|
||||
|
||||
|
|
@ -221,11 +217,10 @@ struct ohci_regs {
|
|||
#define OHCI_INTR_OC (1 << 30) /* ownership change */
|
||||
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
|
||||
|
||||
|
||||
/* Virtual Root HUB */
|
||||
struct virt_root_hub {
|
||||
int devnum; /* Address of Root Hub endpoint */
|
||||
void *dev; /* was urb */
|
||||
int devnum; /* Address of Root Hub endpoint */
|
||||
void *dev; /* was urb */
|
||||
void *int_addr;
|
||||
int send;
|
||||
int interval;
|
||||
|
|
@ -288,52 +283,52 @@ struct virt_root_hub {
|
|||
/* OHCI ROOT HUB REGISTER MASKS */
|
||||
|
||||
/* roothub.portstatus [i] bits */
|
||||
#define RH_PS_CCS 0x00000001 /* current connect status */
|
||||
#define RH_PS_PES 0x00000002 /* port enable status*/
|
||||
#define RH_PS_PSS 0x00000004 /* port suspend status */
|
||||
#define RH_PS_POCI 0x00000008 /* port over current indicator */
|
||||
#define RH_PS_PRS 0x00000010 /* port reset status */
|
||||
#define RH_PS_PPS 0x00000100 /* port power status */
|
||||
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
|
||||
#define RH_PS_CSC 0x00010000 /* connect status change */
|
||||
#define RH_PS_PESC 0x00020000 /* port enable status change */
|
||||
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
|
||||
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
|
||||
#define RH_PS_PRSC 0x00100000 /* port reset status change */
|
||||
#define RH_PS_CCS 0x00000001 /* current connect status */
|
||||
#define RH_PS_PES 0x00000002 /* port enable status */
|
||||
#define RH_PS_PSS 0x00000004 /* port suspend status */
|
||||
#define RH_PS_POCI 0x00000008 /* port over current indicator */
|
||||
#define RH_PS_PRS 0x00000010 /* port reset status */
|
||||
#define RH_PS_PPS 0x00000100 /* port power status */
|
||||
#define RH_PS_LSDA 0x00000200 /* low speed device attached */
|
||||
#define RH_PS_CSC 0x00010000 /* connect status change */
|
||||
#define RH_PS_PESC 0x00020000 /* port enable status change */
|
||||
#define RH_PS_PSSC 0x00040000 /* port suspend status change */
|
||||
#define RH_PS_OCIC 0x00080000 /* over current indicator change */
|
||||
#define RH_PS_PRSC 0x00100000 /* port reset status change */
|
||||
|
||||
/* roothub.status bits */
|
||||
#define RH_HS_LPS 0x00000001 /* local power status */
|
||||
#define RH_HS_OCI 0x00000002 /* over current indicator */
|
||||
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
|
||||
#define RH_HS_LPSC 0x00010000 /* local power status change */
|
||||
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
|
||||
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
|
||||
#define RH_HS_LPS 0x00000001 /* local power status */
|
||||
#define RH_HS_OCI 0x00000002 /* over current indicator */
|
||||
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
|
||||
#define RH_HS_LPSC 0x00010000 /* local power status change */
|
||||
#define RH_HS_OCIC 0x00020000 /* over current indicator change */
|
||||
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
|
||||
|
||||
/* roothub.b masks */
|
||||
#define RH_B_DR 0x0000ffff /* device removable flags */
|
||||
#define RH_B_PPCM 0xffff0000 /* port power control mask */
|
||||
#define RH_B_DR 0x0000ffff /* device removable flags */
|
||||
#define RH_B_PPCM 0xffff0000 /* port power control mask */
|
||||
|
||||
/* roothub.a masks */
|
||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
|
||||
#define RH_A_PSM (1 << 8) /* power switching mode */
|
||||
#define RH_A_NPS (1 << 9) /* no power switching */
|
||||
#define RH_A_DT (1 << 10) /* device type (mbz) */
|
||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */
|
||||
#define RH_A_NOCP (1 << 12) /* no over current protection */
|
||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
|
||||
#define RH_A_NDP (0xff << 0) /* number of downstream ports */
|
||||
#define RH_A_PSM (1 << 8) /* power switching mode */
|
||||
#define RH_A_NPS (1 << 9) /* no power switching */
|
||||
#define RH_A_DT (1 << 10) /* device type (mbz) */
|
||||
#define RH_A_OCPM (1 << 11) /* over current protection mode */
|
||||
#define RH_A_NOCP (1 << 12) /* no over current protection */
|
||||
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
|
||||
|
||||
/* urb */
|
||||
#define N_URB_TD 48
|
||||
typedef struct
|
||||
{
|
||||
ed_t *ed;
|
||||
__u16 length; /* number of tds associated with this request */
|
||||
__u16 td_cnt; /* number of tds already serviced */
|
||||
int state;
|
||||
struct urb_priv {
|
||||
struct ed *ed;
|
||||
__u16 length; /* number of tds associated with this request */
|
||||
__u16 td_cnt; /* number of tds already serviced */
|
||||
int state;
|
||||
unsigned long pipe;
|
||||
int actual_length;
|
||||
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
|
||||
} urb_priv_t;
|
||||
struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs
|
||||
associated with this request */
|
||||
};
|
||||
#define URB_DEL 1
|
||||
|
||||
/*
|
||||
|
|
@ -344,7 +339,7 @@ typedef struct
|
|||
*/
|
||||
|
||||
|
||||
typedef struct ohci {
|
||||
struct ohci {
|
||||
struct ohci_hcca *hcca; /* hcca */
|
||||
/*dma_addr_t hcca_dma; */
|
||||
|
||||
|
|
@ -355,29 +350,29 @@ typedef struct ohci {
|
|||
|
||||
struct ohci_regs *regs; /* OHCI controller's memory */
|
||||
|
||||
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
|
||||
ed_t *ed_bulktail; /* last endpoint of bulk list */
|
||||
ed_t *ed_controltail; /* last endpoint of control list */
|
||||
struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */
|
||||
struct ed *ed_bulktail; /* last endpoint of bulk list */
|
||||
struct ed *ed_controltail; /* last endpoint of control list */
|
||||
int intrstatus;
|
||||
__u32 hc_control; /* copy of the hc control reg */
|
||||
struct usb_device *dev[32];
|
||||
struct virt_root_hub rh;
|
||||
|
||||
const char *slot_name;
|
||||
} ohci_t;
|
||||
};
|
||||
|
||||
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
|
||||
|
||||
struct ohci_device {
|
||||
ed_t ed[NUM_EDS];
|
||||
struct ed ed[NUM_EDS];
|
||||
int ed_cnt;
|
||||
};
|
||||
|
||||
/* hcd */
|
||||
/* endpoint */
|
||||
static int ep_link (ohci_t * ohci, ed_t * ed);
|
||||
static int ep_unlink (ohci_t * ohci, ed_t * ed);
|
||||
static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
|
||||
static int ep_link(struct ohci *ohci, struct ed *ed);
|
||||
static int ep_unlink(struct ohci *ohci, struct ed *ed);
|
||||
static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
|
|
@ -385,13 +380,13 @@ static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
|
|||
#define NUM_TD 64
|
||||
|
||||
/* +1 so we can align the storage */
|
||||
td_t gtd[NUM_TD + 1];
|
||||
struct td gtd[NUM_TD + 1];
|
||||
|
||||
/* pointers to aligned storage */
|
||||
td_t *ptd;
|
||||
struct td *ptd;
|
||||
|
||||
/* TDs ... */
|
||||
static inline struct td *td_alloc (struct usb_device *usb_dev)
|
||||
static inline struct td *td_alloc(struct usb_device *usb_dev)
|
||||
{
|
||||
int i;
|
||||
struct td *td;
|
||||
|
|
@ -408,7 +403,7 @@ static inline struct td *td_alloc (struct usb_device *usb_dev)
|
|||
return td;
|
||||
}
|
||||
|
||||
static inline void ed_free (struct ed *ed)
|
||||
static inline void ed_free(struct ed *ed)
|
||||
{
|
||||
ed->usb_dev = NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
|
||||
|
||||
.globl _start
|
||||
_start: b start_code
|
||||
_start: b start_code
|
||||
ldr pc, _undefined_instruction
|
||||
ldr pc, _software_interrupt
|
||||
ldr pc, _prefetch_abort
|
||||
|
|
@ -109,13 +109,13 @@ start_code:
|
|||
/*
|
||||
* set the cpu to SVC32 mode
|
||||
*/
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x1f
|
||||
orr r0,r0,#0xd3
|
||||
msr cpsr,r0
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1f
|
||||
orr r0, r0, #0xd3
|
||||
msr cpsr, r0
|
||||
|
||||
bl coloured_LED_init
|
||||
bl red_LED_on
|
||||
bl coloured_LED_init
|
||||
bl red_LED_on
|
||||
|
||||
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
|
||||
/*
|
||||
|
|
@ -135,19 +135,19 @@ copyex:
|
|||
/* turn off the watchdog */
|
||||
|
||||
# if defined(CONFIG_S3C2400)
|
||||
# define pWTCON 0x15300000
|
||||
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
||||
# define pWTCON 0x15300000
|
||||
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
||||
# define CLKDIVN 0x14800014 /* clock divisor register */
|
||||
#else
|
||||
# define pWTCON 0x53000000
|
||||
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
||||
# define pWTCON 0x53000000
|
||||
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
||||
# define INTSUBMSK 0x4A00001C
|
||||
# define CLKDIVN 0x4C000014 /* clock divisor register */
|
||||
# endif
|
||||
|
||||
ldr r0, =pWTCON
|
||||
mov r1, #0x0
|
||||
str r1, [r0]
|
||||
ldr r0, =pWTCON
|
||||
mov r1, #0x0
|
||||
str r1, [r0]
|
||||
|
||||
/*
|
||||
* mask all IRQs by setting all bits in the INTMR - default
|
||||
|
|
@ -180,8 +180,8 @@ copyex:
|
|||
relocate: /* relocate U-Boot to RAM */
|
||||
adr r0, _start /* r0 <- current position of code */
|
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
|
|
@ -198,8 +198,8 @@ copy_loop:
|
|||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
|
||||
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
|
||||
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
|
||||
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
|
||||
#endif
|
||||
|
|
@ -297,8 +297,8 @@ cpu_init_crit:
|
|||
#define S_R1 4
|
||||
#define S_R0 0
|
||||
|
||||
#define MODE_SVC 0x13
|
||||
#define I_BIT 0x80
|
||||
#define MODE_SVC 0x13
|
||||
#define I_BIT 0x80
|
||||
|
||||
/*
|
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
||||
|
|
@ -311,7 +311,8 @@ cpu_init_crit:
|
|||
ldr r2, _armboot_start
|
||||
sub r2, r2, #(CONFIG_STACKSIZE)
|
||||
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
|
||||
/* set base 2 words into abort stack */
|
||||
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
||||
ldmia r2, {r2 - r3} @ get pc, cpsr
|
||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
|
||||
|
||||
|
|
@ -324,12 +325,12 @@ cpu_init_crit:
|
|||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE
|
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r7, sp, #S_PC
|
||||
stmdb r7, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r7, #0] @ Save calling PC
|
||||
mrs r6, spsr
|
||||
str r6, [r7, #4] @ Save CPSR
|
||||
str r0, [r7, #8] @ Save OLD_R0
|
||||
add r7, sp, #S_PC
|
||||
stmdb r7, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r7, #0] @ Save calling PC
|
||||
mrs r6, spsr
|
||||
str r6, [r7, #4] @ Save CPSR
|
||||
str r0, [r7, #8] @ Save OLD_R0
|
||||
mov r0, sp
|
||||
.endm
|
||||
|
||||
|
|
@ -338,18 +339,20 @@ cpu_init_crit:
|
|||
mov r0, r0
|
||||
ldr lr, [sp, #S_PC] @ Get PC
|
||||
add sp, sp, #S_FRAME_SIZE
|
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
/* return & move spsr_svc into cpsr */
|
||||
subs pc, lr, #4
|
||||
.endm
|
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_start @ setup our mode stack
|
||||
sub r13, r13, #(CONFIG_STACKSIZE)
|
||||
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
|
||||
/* reserve a couple spots in abort stack */
|
||||
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr
|
||||
str lr, [r13, #4]
|
||||
str lr, [r13, #4]
|
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode
|
||||
@ msr spsr_c, r13
|
||||
|
|
|
|||
Loading…
Reference in a new issue