2014-06-23 22:15:55 +00:00
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/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <errno.h>
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#include <asm/io.h>
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2015-01-06 21:19:02 +00:00
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/fsl_mc_sys.h>
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2015-03-19 16:20:45 +00:00
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#include <fsl-mc/fsl_mc_private.h>
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2015-01-06 21:19:02 +00:00
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#include <fsl-mc/fsl_dpmng.h>
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2015-03-19 16:20:43 +00:00
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#include <fsl_debug_server.h>
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2015-03-19 16:20:45 +00:00
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#include <fsl-mc/fsl_dprc.h>
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#include <fsl-mc/fsl_dpio.h>
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#include <fsl-mc/fsl_qbman_portal.h>
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2014-06-23 22:15:55 +00:00
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2015-03-21 02:28:18 +00:00
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#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
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#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
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#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
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#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
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#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
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2014-06-23 22:15:55 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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static int mc_boot_status;
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2015-03-19 16:20:45 +00:00
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struct fsl_mc_io *dflt_mc_io = NULL;
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uint16_t dflt_dprc_handle = 0;
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struct fsl_dpbp_obj *dflt_dpbp = NULL;
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struct fsl_dpio_obj *dflt_dpio = NULL;
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2015-03-21 02:28:18 +00:00
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uint16_t dflt_dpio_handle = 0;
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#ifdef DEBUG
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void dump_ram_words(const char *title, void *addr)
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{
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int i;
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uint32_t *words = addr;
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printf("Dumping beginning of %s (%p):\n", title, addr);
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for (i = 0; i < 16; i++)
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printf("%#x ", words[i]);
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printf("\n");
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}
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2014-06-23 22:15:55 +00:00
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2015-03-21 02:28:18 +00:00
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void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
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{
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printf("MC CCSR registers:\n"
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"reg_gcr1 %#x\n"
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"reg_gsr %#x\n"
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"reg_sicbalr %#x\n"
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"reg_sicbahr %#x\n"
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"reg_sicapr %#x\n"
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"reg_mcfbalr %#x\n"
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"reg_mcfbahr %#x\n"
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"reg_mcfapr %#x\n"
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"reg_psr %#x\n",
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mc_ccsr_regs->reg_gcr1,
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mc_ccsr_regs->reg_gsr,
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mc_ccsr_regs->reg_sicbalr,
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mc_ccsr_regs->reg_sicbahr,
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mc_ccsr_regs->reg_sicapr,
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mc_ccsr_regs->reg_mcfbalr,
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mc_ccsr_regs->reg_mcfbahr,
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mc_ccsr_regs->reg_mcfapr,
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mc_ccsr_regs->reg_psr);
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}
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#else
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#define dump_ram_words(title, addr)
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#define dump_mc_ccsr_regs(mc_ccsr_regs)
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#endif /* DEBUG */
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#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
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2014-06-23 22:15:55 +00:00
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/**
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* Copying MC firmware or DPL image to DDR
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*/
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static int mc_copy_image(const char *title,
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2015-01-06 21:19:02 +00:00
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u64 image_addr, u32 image_size, u64 mc_ram_addr)
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2014-06-23 22:15:55 +00:00
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{
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debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
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memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
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2015-03-21 02:28:18 +00:00
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flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
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2014-06-23 22:15:55 +00:00
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return 0;
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}
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/**
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* MC firmware FIT image parser checks if the image is in FIT
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* format, verifies integrity of the image and calculates
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* raw image address and size values.
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2015-01-06 21:19:02 +00:00
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* Returns 0 on success and a negative errno on error.
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2014-06-23 22:15:55 +00:00
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* task fail.
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**/
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int parse_mc_firmware_fit_image(const void **raw_image_addr,
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size_t *raw_image_size)
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{
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int format;
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void *fit_hdr;
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int node_offset;
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const void *data;
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size_t size;
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const char *uname = "firmware";
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2015-01-06 21:19:02 +00:00
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/* Check if the image is in NOR flash */
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2014-06-23 22:15:55 +00:00
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#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR
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fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR;
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#else
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#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined"
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#endif
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/* Check if Image is in FIT format */
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format = genimg_get_format(fit_hdr);
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if (format != IMAGE_FORMAT_FIT) {
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2015-01-06 21:19:02 +00:00
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printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n");
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return -EINVAL;
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2014-06-23 22:15:55 +00:00
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}
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if (!fit_check_format(fit_hdr)) {
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2015-01-06 21:19:02 +00:00
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printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n");
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return -EINVAL;
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2014-06-23 22:15:55 +00:00
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}
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node_offset = fit_image_get_node(fit_hdr, uname);
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if (node_offset < 0) {
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2015-01-06 21:19:02 +00:00
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printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n");
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return -ENOENT;
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2014-06-23 22:15:55 +00:00
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}
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/* Verify MC firmware image */
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if (!(fit_image_verify(fit_hdr, node_offset))) {
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2015-01-06 21:19:02 +00:00
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printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n");
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return -EINVAL;
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2014-06-23 22:15:55 +00:00
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}
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/* Get address and size of raw image */
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fit_image_get_data(fit_hdr, node_offset, &data, &size);
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*raw_image_addr = data;
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*raw_image_size = size;
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return 0;
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}
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2015-03-21 02:28:18 +00:00
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#endif
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/*
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* Calculates the values to be used to specify the address range
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* for the MC private DRAM block, in the MCFBALR/MCFBAHR registers.
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* It returns the highest 512MB-aligned address within the given
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* address range, in '*aligned_base_addr', and the number of 256 MiB
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* blocks in it, in 'num_256mb_blocks'.
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*/
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static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
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size_t mc_ram_size,
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u64 *aligned_base_addr,
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u8 *num_256mb_blocks)
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{
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u64 addr;
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u16 num_blocks;
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if (mc_ram_size % MC_RAM_SIZE_ALIGNMENT != 0) {
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printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
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mc_ram_size);
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return -EINVAL;
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}
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num_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
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if (num_blocks < 1 || num_blocks > 0xff) {
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printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
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mc_ram_size);
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return -EINVAL;
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}
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addr = (mc_private_ram_start_addr + mc_ram_size - 1) &
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MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
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if (addr < mc_private_ram_start_addr) {
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printf("fsl-mc: ERROR: bad start address %#llx\n",
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mc_private_ram_start_addr);
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return -EFAULT;
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}
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*aligned_base_addr = addr;
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*num_256mb_blocks = num_blocks;
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return 0;
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}
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static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size)
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{
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u64 mc_dpc_offset;
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#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
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int error;
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void *dpc_fdt_hdr;
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int dpc_size;
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#endif
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#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
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BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
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CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
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mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET;
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#else
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#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
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#endif
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/*
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* Load the MC DPC blob in the MC private DRAM block:
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*/
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#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
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printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
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#else
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/*
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* Get address and size of the DPC blob stored in flash:
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*/
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#ifdef CONFIG_SYS_LS_MC_DPC_IN_NOR
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dpc_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPC_ADDR;
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#else
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#error "No CONFIG_SYS_LS_MC_DPC_IN_xxx defined"
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#endif
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error = fdt_check_header(dpc_fdt_hdr);
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if (error != 0) {
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/*
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* Don't return with error here, since the MC firmware can
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* still boot without a DPC
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*/
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printf("fsl-mc: WARNING: No DPC image found\n");
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return 0;
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}
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dpc_size = fdt_totalsize(dpc_fdt_hdr);
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if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) {
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printf("fsl-mc: ERROR: Bad DPC image (too large: %d)\n",
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dpc_size);
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return -EINVAL;
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}
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mc_copy_image("MC DPC blob",
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(u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
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#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
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dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
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return 0;
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}
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static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size)
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{
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u64 mc_dpl_offset;
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#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
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int error;
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void *dpl_fdt_hdr;
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int dpl_size;
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#endif
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#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
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BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
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CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
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mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET;
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#else
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#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
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#endif
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/*
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* Load the MC DPL blob in the MC private DRAM block:
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*/
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#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
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printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
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#else
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/*
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* Get address and size of the DPL blob stored in flash:
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*/
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#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR
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dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR;
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#else
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#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined"
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#endif
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error = fdt_check_header(dpl_fdt_hdr);
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if (error != 0) {
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printf("fsl-mc: ERROR: Bad DPL image (bad header)\n");
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return error;
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}
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dpl_size = fdt_totalsize(dpl_fdt_hdr);
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if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) {
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printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n",
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dpl_size);
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return -EINVAL;
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}
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mc_copy_image("MC DPL blob",
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(u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
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#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
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dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
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return 0;
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}
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/**
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* Return the MC boot timeout value in milliseconds
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*/
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static unsigned long get_mc_boot_timeout_ms(void)
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{
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unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
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char *timeout_ms_env_var = getenv(MC_BOOT_TIMEOUT_ENV_VAR);
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if (timeout_ms_env_var) {
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timeout_ms = simple_strtoul(timeout_ms_env_var, NULL, 10);
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if (timeout_ms == 0) {
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printf("fsl-mc: WARNING: Invalid value for \'"
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MC_BOOT_TIMEOUT_ENV_VAR
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"\' environment variable: %lu\n",
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timeout_ms);
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timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS;
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}
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}
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return timeout_ms;
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}
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static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
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{
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u32 reg_gsr;
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u32 mc_fw_boot_status;
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unsigned long timeout_ms = get_mc_boot_timeout_ms();
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struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
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dmb();
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|
|
debug("Polling mc_ccsr_regs->reg_gsr ...\n");
|
|
|
|
assert(timeout_ms > 0);
|
|
|
|
for (;;) {
|
|
|
|
udelay(1000); /* throttle polling */
|
|
|
|
reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
|
|
|
|
mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
|
|
|
|
if (mc_fw_boot_status & 0x1)
|
|
|
|
break;
|
|
|
|
|
|
|
|
timeout_ms--;
|
|
|
|
if (timeout_ms == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout_ms == 0) {
|
|
|
|
if (booting_mc)
|
|
|
|
printf("fsl-mc: timeout booting management complex firmware\n");
|
|
|
|
else
|
|
|
|
printf("fsl-mc: timeout deploying data path layout\n");
|
|
|
|
|
|
|
|
/* TODO: Get an error status from an MC CCSR register */
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mc_fw_boot_status != 0x1) {
|
|
|
|
/*
|
|
|
|
* TODO: Identify critical errors from the GSR register's FS
|
|
|
|
* field and for those errors, set error to -ENODEV or other
|
|
|
|
* appropriate errno, so that the status property is set to
|
|
|
|
* failure in the fsl,dprc device tree node.
|
|
|
|
*/
|
|
|
|
if (booting_mc) {
|
|
|
|
printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n",
|
|
|
|
reg_gsr);
|
|
|
|
} else {
|
|
|
|
printf("fsl-mc: WARNING: Data path layout deployed with error (GSR: %#x)\n",
|
|
|
|
reg_gsr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
*final_reg_gsr = reg_gsr;
|
|
|
|
return 0;
|
|
|
|
}
|
2014-06-23 22:15:55 +00:00
|
|
|
|
2015-03-19 16:20:45 +00:00
|
|
|
int mc_init(void)
|
2014-06-23 22:15:55 +00:00
|
|
|
{
|
|
|
|
int error = 0;
|
2015-03-19 16:20:45 +00:00
|
|
|
int portal_id = 0;
|
2014-06-23 22:15:55 +00:00
|
|
|
struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
|
|
|
|
u64 mc_ram_addr;
|
|
|
|
u32 reg_gsr;
|
2015-03-21 02:28:18 +00:00
|
|
|
u32 reg_mcfbalr;
|
|
|
|
#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
|
2014-06-23 22:15:55 +00:00
|
|
|
const void *raw_image_addr;
|
|
|
|
size_t raw_image_size = 0;
|
2015-03-21 02:28:18 +00:00
|
|
|
#endif
|
2015-01-06 21:19:02 +00:00
|
|
|
struct mc_version mc_ver_info;
|
2015-03-21 02:28:18 +00:00
|
|
|
u64 mc_ram_aligned_base_addr;
|
|
|
|
u8 mc_ram_num_256mb_blocks;
|
|
|
|
size_t mc_ram_size = mc_get_dram_block_size();
|
2014-06-23 22:15:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The MC private DRAM block was already carved at the end of DRAM
|
|
|
|
* by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
|
|
|
|
*/
|
|
|
|
if (gd->bd->bi_dram[1].start) {
|
|
|
|
mc_ram_addr =
|
|
|
|
gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
|
|
|
|
} else {
|
|
|
|
mc_ram_addr =
|
|
|
|
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
|
|
|
|
}
|
|
|
|
|
2015-03-19 16:20:43 +00:00
|
|
|
#ifdef CONFIG_FSL_DEBUG_SERVER
|
2015-03-21 02:28:18 +00:00
|
|
|
/*
|
|
|
|
* FIXME: I don't think this is right. See get_dram_size_to_hide()
|
|
|
|
*/
|
2015-03-19 16:20:43 +00:00
|
|
|
mc_ram_addr -= debug_server_get_dram_block_size();
|
|
|
|
#endif
|
2015-03-21 02:28:18 +00:00
|
|
|
|
|
|
|
error = calculate_mc_private_ram_params(mc_ram_addr,
|
|
|
|
mc_ram_size,
|
|
|
|
&mc_ram_aligned_base_addr,
|
|
|
|
&mc_ram_num_256mb_blocks);
|
|
|
|
if (error != 0)
|
|
|
|
goto out;
|
|
|
|
|
2014-06-23 22:15:55 +00:00
|
|
|
/*
|
|
|
|
* Management Complex cores should be held at reset out of POR.
|
|
|
|
* U-boot should be the first software to touch MC. To be safe,
|
|
|
|
* we reset all cores again by setting GCR1 to 0. It doesn't do
|
|
|
|
* anything if they are held at reset. After we setup the firmware
|
|
|
|
* we kick off MC by deasserting the reset bit for core 0, and
|
|
|
|
* deasserting the reset bits for Command Portal Managers.
|
|
|
|
* The stop bits are not touched here. They are used to stop the
|
|
|
|
* cores when they are active. Setting stop bits doesn't stop the
|
|
|
|
* cores from fetching instructions when they are released from
|
|
|
|
* reset.
|
|
|
|
*/
|
|
|
|
out_le32(&mc_ccsr_regs->reg_gcr1, 0);
|
|
|
|
dmb();
|
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
|
|
|
|
printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
|
|
|
|
#else
|
2014-06-23 22:15:55 +00:00
|
|
|
error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size);
|
|
|
|
if (error != 0)
|
|
|
|
goto out;
|
|
|
|
/*
|
|
|
|
* Load the MC FW at the beginning of the MC private DRAM block:
|
|
|
|
*/
|
2015-01-06 21:19:02 +00:00
|
|
|
mc_copy_image("MC Firmware",
|
|
|
|
(u64)raw_image_addr, raw_image_size, mc_ram_addr);
|
|
|
|
#endif
|
2015-03-21 02:28:18 +00:00
|
|
|
dump_ram_words("firmware", (void *)mc_ram_addr);
|
2015-01-06 21:19:02 +00:00
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
error = load_mc_dpc(mc_ram_addr, mc_ram_size);
|
|
|
|
if (error != 0)
|
2015-01-06 21:19:02 +00:00
|
|
|
goto out;
|
2014-06-23 22:15:55 +00:00
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
error = load_mc_dpl(mc_ram_addr, mc_ram_size);
|
|
|
|
if (error != 0)
|
2014-06-23 22:15:55 +00:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
|
2015-03-21 02:28:18 +00:00
|
|
|
dump_mc_ccsr_regs(mc_ccsr_regs);
|
2014-06-23 22:15:55 +00:00
|
|
|
|
|
|
|
/*
|
2015-03-21 02:28:18 +00:00
|
|
|
* Tell MC what is the address range of the DRAM block assigned to it:
|
2014-06-23 22:15:55 +00:00
|
|
|
*/
|
2015-03-21 02:28:18 +00:00
|
|
|
reg_mcfbalr = (u32)mc_ram_aligned_base_addr |
|
|
|
|
(mc_ram_num_256mb_blocks - 1);
|
|
|
|
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
|
|
|
|
out_le32(&mc_ccsr_regs->reg_mcfbahr,
|
|
|
|
(u32)(mc_ram_aligned_base_addr >> 32));
|
2014-06-23 22:15:55 +00:00
|
|
|
out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK);
|
|
|
|
|
|
|
|
/*
|
2015-03-21 02:28:18 +00:00
|
|
|
* Tell the MC that we want delayed DPL deployment.
|
2014-06-23 22:15:55 +00:00
|
|
|
*/
|
2015-03-21 02:28:18 +00:00
|
|
|
out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
|
2014-06-23 22:15:55 +00:00
|
|
|
|
2015-01-06 21:19:02 +00:00
|
|
|
printf("\nfsl-mc: Booting Management Complex ...\n");
|
|
|
|
|
2014-06-23 22:15:55 +00:00
|
|
|
/*
|
|
|
|
* Deassert reset and release MC core 0 to run
|
|
|
|
*/
|
|
|
|
out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
|
2015-03-21 02:28:18 +00:00
|
|
|
error = wait_for_mc(true, ®_gsr);
|
|
|
|
if (error != 0)
|
2014-06-23 22:15:55 +00:00
|
|
|
goto out;
|
|
|
|
|
2015-01-06 21:19:02 +00:00
|
|
|
/*
|
|
|
|
* TODO: need to obtain the portal_id for the root container from the
|
|
|
|
* DPL
|
|
|
|
*/
|
|
|
|
portal_id = 0;
|
|
|
|
|
|
|
|
/*
|
2015-03-19 16:20:45 +00:00
|
|
|
* Initialize the global default MC portal
|
|
|
|
* And check that the MC firmware is responding portal commands:
|
2015-01-06 21:19:02 +00:00
|
|
|
*/
|
2015-03-19 16:20:45 +00:00
|
|
|
dflt_mc_io = (struct fsl_mc_io *)malloc(sizeof(struct fsl_mc_io));
|
|
|
|
if (!dflt_mc_io) {
|
|
|
|
printf(" No memory: malloc() failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
|
2015-01-06 21:19:02 +00:00
|
|
|
debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
|
2015-03-19 16:20:45 +00:00
|
|
|
portal_id, dflt_mc_io->mmio_regs);
|
2015-01-06 21:19:02 +00:00
|
|
|
|
2015-03-19 16:20:45 +00:00
|
|
|
error = mc_get_version(dflt_mc_io, &mc_ver_info);
|
2015-01-06 21:19:02 +00:00
|
|
|
if (error != 0) {
|
|
|
|
printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
|
|
|
|
error);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (MC_VER_MAJOR != mc_ver_info.major)
|
|
|
|
printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n",
|
|
|
|
mc_ver_info.major, MC_VER_MAJOR);
|
|
|
|
|
|
|
|
if (MC_VER_MINOR != mc_ver_info.minor)
|
|
|
|
printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n",
|
|
|
|
mc_ver_info.minor, MC_VER_MINOR);
|
|
|
|
|
|
|
|
printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
|
|
|
|
mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
|
2015-03-21 02:28:18 +00:00
|
|
|
reg_gsr & GSR_FS_MASK);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Tell the MC to deploy the DPL:
|
|
|
|
*/
|
|
|
|
out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
|
|
|
|
printf("\nfsl-mc: Deploying data path layout ...\n");
|
|
|
|
error = wait_for_mc(false, ®_gsr);
|
|
|
|
if (error != 0)
|
|
|
|
goto out;
|
2014-06-23 22:15:55 +00:00
|
|
|
out:
|
|
|
|
if (error != 0)
|
|
|
|
mc_boot_status = -error;
|
|
|
|
else
|
|
|
|
mc_boot_status = 0;
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
int get_mc_boot_status(void)
|
|
|
|
{
|
|
|
|
return mc_boot_status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Return the actual size of the MC private DRAM block.
|
|
|
|
*/
|
|
|
|
unsigned long mc_get_dram_block_size(void)
|
|
|
|
{
|
2015-03-21 02:28:18 +00:00
|
|
|
unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
|
|
|
|
|
|
|
|
char *dram_block_size_env_var = getenv(MC_MEM_SIZE_ENV_VAR);
|
|
|
|
|
|
|
|
if (dram_block_size_env_var) {
|
|
|
|
dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
|
|
|
|
10);
|
|
|
|
|
|
|
|
if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
|
|
|
|
printf("fsl-mc: WARNING: Invalid value for \'"
|
|
|
|
MC_MEM_SIZE_ENV_VAR
|
|
|
|
"\' environment variable: %lu\n",
|
|
|
|
dram_block_size);
|
|
|
|
|
|
|
|
dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return dram_block_size;
|
2014-06-23 22:15:55 +00:00
|
|
|
}
|
2015-03-19 16:20:45 +00:00
|
|
|
|
|
|
|
int dpio_init(struct dprc_obj_desc obj_desc)
|
|
|
|
{
|
|
|
|
struct qbman_swp_desc p_des;
|
|
|
|
struct dpio_attr attr;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
dflt_dpio = (struct fsl_dpio_obj *)malloc(sizeof(struct fsl_dpio_obj));
|
|
|
|
if (!dflt_dpio) {
|
|
|
|
printf(" No memory: malloc() failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
dflt_dpio->dpio_id = obj_desc.id;
|
|
|
|
|
|
|
|
err = dpio_open(dflt_mc_io, obj_desc.id, &dflt_dpio_handle);
|
|
|
|
if (err) {
|
|
|
|
printf("dpio_open() failed\n");
|
|
|
|
goto err_open;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = dpio_get_attributes(dflt_mc_io, dflt_dpio_handle, &attr);
|
|
|
|
if (err) {
|
|
|
|
printf("dpio_get_attributes() failed %d\n", err);
|
|
|
|
goto err_get_attr;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = dpio_enable(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
if (err) {
|
|
|
|
printf("dpio_enable() failed %d\n", err);
|
|
|
|
goto err_get_enable;
|
|
|
|
}
|
|
|
|
debug("ce_paddr=0x%llx, ci_paddr=0x%llx, portalid=%d, prios=%d\n",
|
|
|
|
attr.qbman_portal_ce_paddr,
|
|
|
|
attr.qbman_portal_ci_paddr,
|
|
|
|
attr.qbman_portal_id,
|
|
|
|
attr.num_priorities);
|
|
|
|
|
|
|
|
p_des.cena_bar = (void *)attr.qbman_portal_ce_paddr;
|
|
|
|
p_des.cinh_bar = (void *)attr.qbman_portal_ci_paddr;
|
|
|
|
|
|
|
|
dflt_dpio->sw_portal = qbman_swp_init(&p_des);
|
|
|
|
if (dflt_dpio->sw_portal == NULL) {
|
|
|
|
printf("qbman_swp_init() failed\n");
|
|
|
|
goto err_get_swp_init;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_get_swp_init:
|
|
|
|
err_get_enable:
|
|
|
|
dpio_disable(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
err_get_attr:
|
|
|
|
dpio_close(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
err_open:
|
|
|
|
free(dflt_dpio);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dpbp_init(struct dprc_obj_desc obj_desc)
|
|
|
|
{
|
|
|
|
dflt_dpbp = (struct fsl_dpbp_obj *)malloc(sizeof(struct fsl_dpbp_obj));
|
|
|
|
if (!dflt_dpbp) {
|
|
|
|
printf(" No memory: malloc() failed\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
dflt_dpbp->dpbp_attr.id = obj_desc.id;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-19 16:20:46 +00:00
|
|
|
int dprc_init_container_obj(struct dprc_obj_desc obj_desc, uint16_t dprc_handle)
|
2015-03-19 16:20:45 +00:00
|
|
|
{
|
2015-03-19 16:20:46 +00:00
|
|
|
int error = 0, state = 0;
|
|
|
|
struct dprc_endpoint dpni_endpoint, dpmac_endpoint;
|
2015-03-19 16:20:45 +00:00
|
|
|
if (!strcmp(obj_desc.type, "dpbp")) {
|
|
|
|
if (!dflt_dpbp) {
|
|
|
|
error = dpbp_init(obj_desc);
|
|
|
|
if (error < 0)
|
|
|
|
printf("dpbp_init failed\n");
|
|
|
|
}
|
|
|
|
} else if (!strcmp(obj_desc.type, "dpio")) {
|
|
|
|
if (!dflt_dpio) {
|
|
|
|
error = dpio_init(obj_desc);
|
|
|
|
if (error < 0)
|
|
|
|
printf("dpio_init failed\n");
|
|
|
|
}
|
2015-03-19 16:20:46 +00:00
|
|
|
} else if (!strcmp(obj_desc.type, "dpni")) {
|
|
|
|
strcpy(dpni_endpoint.type, obj_desc.type);
|
|
|
|
dpni_endpoint.id = obj_desc.id;
|
|
|
|
error = dprc_get_connection(dflt_mc_io, dprc_handle,
|
|
|
|
&dpni_endpoint, &dpmac_endpoint, &state);
|
|
|
|
if (!strcmp(dpmac_endpoint.type, "dpmac"))
|
|
|
|
error = ldpaa_eth_init(obj_desc);
|
|
|
|
if (error < 0)
|
|
|
|
printf("ldpaa_eth_init failed\n");
|
2015-03-19 16:20:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dprc_scan_container_obj(uint16_t dprc_handle, char *obj_type, int i)
|
|
|
|
{
|
|
|
|
int error = 0;
|
|
|
|
struct dprc_obj_desc obj_desc;
|
|
|
|
|
|
|
|
memset((void *)&obj_desc, 0x00, sizeof(struct dprc_obj_desc));
|
|
|
|
|
|
|
|
error = dprc_get_obj(dflt_mc_io, dprc_handle,
|
|
|
|
i, &obj_desc);
|
|
|
|
if (error < 0) {
|
|
|
|
printf("dprc_get_obj(i=%d) failed: %d\n",
|
|
|
|
i, error);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!strcmp(obj_desc.type, obj_type)) {
|
|
|
|
debug("Discovered object: type %s, id %d, req %s\n",
|
|
|
|
obj_desc.type, obj_desc.id, obj_type);
|
|
|
|
|
2015-03-19 16:20:46 +00:00
|
|
|
error = dprc_init_container_obj(obj_desc, dprc_handle);
|
2015-03-19 16:20:45 +00:00
|
|
|
if (error < 0) {
|
|
|
|
printf("dprc_init_container_obj(i=%d) failed: %d\n",
|
|
|
|
i, error);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
int fsl_mc_ldpaa_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
int i, error = 0;
|
|
|
|
int dprc_opened = 0, container_id;
|
|
|
|
int num_child_objects = 0;
|
|
|
|
|
|
|
|
error = mc_init();
|
2015-03-21 02:28:18 +00:00
|
|
|
if (error < 0)
|
|
|
|
goto error;
|
2015-03-19 16:20:45 +00:00
|
|
|
|
|
|
|
error = dprc_get_container_id(dflt_mc_io, &container_id);
|
|
|
|
if (error < 0) {
|
|
|
|
printf("dprc_get_container_id() failed: %d\n", error);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
debug("fsl-mc: Container id=0x%x\n", container_id);
|
|
|
|
|
|
|
|
error = dprc_open(dflt_mc_io, container_id, &dflt_dprc_handle);
|
|
|
|
if (error < 0) {
|
|
|
|
printf("dprc_open() failed: %d\n", error);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
dprc_opened = true;
|
|
|
|
|
|
|
|
error = dprc_get_obj_count(dflt_mc_io,
|
|
|
|
dflt_dprc_handle,
|
|
|
|
&num_child_objects);
|
|
|
|
if (error < 0) {
|
|
|
|
printf("dprc_get_obj_count() failed: %d\n", error);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
debug("Total child in container %d = %d\n", container_id,
|
|
|
|
num_child_objects);
|
|
|
|
|
|
|
|
if (num_child_objects != 0) {
|
|
|
|
/*
|
|
|
|
* Discover objects currently in the DPRC container in the MC:
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_child_objects; i++)
|
|
|
|
error = dprc_scan_container_obj(dflt_dprc_handle,
|
|
|
|
"dpbp", i);
|
|
|
|
|
|
|
|
for (i = 0; i < num_child_objects; i++)
|
|
|
|
error = dprc_scan_container_obj(dflt_dprc_handle,
|
|
|
|
"dpio", i);
|
|
|
|
|
|
|
|
for (i = 0; i < num_child_objects; i++)
|
|
|
|
error = dprc_scan_container_obj(dflt_dprc_handle,
|
|
|
|
"dpni", i);
|
|
|
|
}
|
|
|
|
error:
|
|
|
|
if (dprc_opened)
|
|
|
|
dprc_close(dflt_mc_io, dflt_dprc_handle);
|
|
|
|
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
void fsl_mc_ldpaa_exit(bd_t *bis)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
if (get_mc_boot_status() == 0) {
|
|
|
|
err = dpio_disable(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
if (err < 0) {
|
|
|
|
printf("dpio_disable() failed: %d\n", err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
err = dpio_reset(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
if (err < 0) {
|
|
|
|
printf("dpio_reset() failed: %d\n", err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
err = dpio_close(dflt_mc_io, dflt_dpio_handle);
|
|
|
|
if (err < 0) {
|
|
|
|
printf("dpio_close() failed: %d\n", err);
|
|
|
|
return;
|
|
|
|
}
|
2015-03-19 16:20:45 +00:00
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
free(dflt_dpio);
|
|
|
|
free(dflt_dpbp);
|
2015-03-19 16:20:45 +00:00
|
|
|
}
|
|
|
|
|
2015-03-21 02:28:18 +00:00
|
|
|
if (dflt_mc_io)
|
|
|
|
free(dflt_mc_io);
|
2015-03-19 16:20:45 +00:00
|
|
|
}
|