u-boot/arch/riscv/cpu/jh7110/Kconfig

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2022 StarFive Technology Co., Ltd.

config STARFIVE_JH7110
	bool
	select ARCH_EARLY_INIT_R
	select CLK_JH7110
	select CPU
	select CPU_RISCV
	select RAM
	select RESET_JH7110
	select SUPPORT_SPL
	select SPL_RAM if SPL
	select SPL_STARFIVE_DDR
	select SYS_CACHE_SHIFT_6
	select SPL_ZERO_MEM_BEFORE_USE
	select PINCTRL_STARFIVE_JH7110
	imply MMC
	imply MMC_BROKEN_CD
	imply MMC_SPI
	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
	imply SIFIVE_CACHE
	imply SIFIVE_CCACHE
	imply SMP
	imply SPI
	imply SPL_CPU
	imply SPL_LOAD_FIT
	imply SPL_OPENSBI
	imply SPL_RISCV_ACLINT
	imply SPL_SYS_MALLOC_CLEAR_ON_INIT
riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 2023-03-29 03:42:18 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`# Copyright (C) 2022 StarFive Technology Co., Ltd.`

			`config STARFIVE_JH7110`
			`bool`
			`select ARCH_EARLY_INIT_R`
			`select CLK_JH7110`
			`select CPU`
			`select CPU_RISCV`
			`select RAM`
			`select RESET_JH7110`
			`select SUPPORT_SPL`
			`select SPL_RAM if SPL`
			`select SPL_STARFIVE_DDR`
riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive SYS_CACHE_SHIFT_6 to enable it. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2023-08-07 08:53:37 +00:00			`select SYS_CACHE_SHIFT_6`
riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2023-08-09 13:11:33 +00:00			`select SPL_ZERO_MEM_BEFORE_USE`
riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 2023-03-29 03:42:18 +00:00			`select PINCTRL_STARFIVE_JH7110`
			`imply MMC`
			`imply MMC_BROKEN_CD`
			`imply MMC_SPI`
			`imply RISCV_TIMER if (RISCV_SMODE \|\| SPL_RISCV_SMODE)`
			`imply SIFIVE_CACHE`
			`imply SIFIVE_CCACHE`
			`imply SMP`
			`imply SPI`
			`imply SPL_CPU`
			`imply SPL_LOAD_FIT`
			`imply SPL_OPENSBI`
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> 2023-06-21 15:11:46 +00:00			`imply SPL_RISCV_ACLINT`
riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 2023-08-24 16:25:20 +00:00			`imply SPL_SYS_MALLOC_CLEAR_ON_INIT`