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u-boot/drivers/ram/k3-ddrss/lpddr4_j721e.h

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ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
ram: k3-ddrss: add auto-generated macros for am62a support The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-10-24 21:53:28 +00:00
* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
*/
ram: k3-ddrss: add auto-generated macros for am62a support The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-10-24 21:53:28 +00:00
#ifndef LPDDR4_J721E_H
#define LPDDR4_J721E_H
#include "lpddr4_j721e_ctl_regs_rw_masks.h"
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:11 +00:00
#define DSLICE_NUM (4U)
#define ASLICE_NUM (1U)
#define DSLICE0_REG_COUNT (140U)
#define DSLICE1_REG_COUNT (140U)
#define DSLICE2_REG_COUNT (140U)
#define DSLICE3_REG_COUNT (140U)
#define ASLICE0_REG_COUNT (52U)
#define PHY_CORE_REG_COUNT (140U)
ram: k3-ddrss: add auto-generated macros for am62a support The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
2022-10-24 21:53:28 +00:00
#endif /* LPDDR4_J721E_H */
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