2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2008-01-14 23:43:33 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2000-2003
|
|
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
|
|
*
|
2012-03-26 21:49:03 +00:00
|
|
|
* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
|
2008-01-14 23:43:33 +00:00
|
|
|
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2019-12-28 17:45:06 +00:00
|
|
|
#include <init.h>
|
2020-10-31 03:38:53 +00:00
|
|
|
#include <asm/global_data.h>
|
2008-01-14 23:43:33 +00:00
|
|
|
#include <asm/immap.h>
|
2012-03-26 21:49:03 +00:00
|
|
|
#include <asm/io.h>
|
2020-05-10 17:40:11 +00:00
|
|
|
#include <linux/delay.h>
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
|
|
|
int checkboard(void)
|
|
|
|
{
|
|
|
|
puts("Board: ");
|
|
|
|
puts("Freescale M52277 EVB\n");
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
|
2017-04-06 18:47:05 +00:00
|
|
|
int dram_init(void)
|
2008-01-14 23:43:33 +00:00
|
|
|
{
|
2008-10-21 15:37:02 +00:00
|
|
|
u32 dramsize;
|
|
|
|
|
|
|
|
#ifdef CONFIG_CF_SBF
|
|
|
|
/*
|
|
|
|
* Serial Boot: The dram is already initialized in start.S
|
|
|
|
* only require to return DRAM size
|
|
|
|
*/
|
|
|
|
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
|
|
|
#else
|
2012-03-26 21:49:03 +00:00
|
|
|
sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
|
|
|
|
gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
|
2008-10-21 15:37:02 +00:00
|
|
|
u32 i;
|
2008-01-14 23:43:33 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
for (i = 0x13; i < 0x20; i++) {
|
|
|
|
if (dramsize == (1 << i))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
i--;
|
|
|
|
|
2012-03-26 21:49:03 +00:00
|
|
|
out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
|
2008-10-21 15:37:02 +00:00
|
|
|
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
|
2008-01-14 23:43:33 +00:00
|
|
|
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
|
|
|
|
out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
/* Issue PALL */
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
/* Issue LEMR */
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
/* Issue PALL */
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
/* Perform two refresh cycles */
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
|
2008-10-21 15:37:02 +00:00
|
|
|
__asm__("nop");
|
2008-01-14 23:43:33 +00:00
|
|
|
|
2012-03-26 21:49:03 +00:00
|
|
|
out_be32(&sdram->sdcr,
|
|
|
|
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
|
2008-01-14 23:43:33 +00:00
|
|
|
|
|
|
|
udelay(100);
|
2008-10-21 15:37:02 +00:00
|
|
|
#endif
|
2017-03-31 14:40:25 +00:00
|
|
|
gd->ram_size = dramsize;
|
|
|
|
|
|
|
|
return 0;
|
2008-01-14 23:43:33 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
int testdram(void)
|
|
|
|
{
|
|
|
|
/* TODO: XXX XXX XXX */
|
|
|
|
printf("DRAM test not implemented!\n");
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|