Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-17 10:18:38 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/dts/k3-am64-mcu.dtsi

113 lines
3.1 KiB
Text
Raw Normal View History

arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
mcu_i2c0: i2c@4900000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04900000 0x00 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
mcu_i2c1: i2c@4910000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04910000 0x00 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
arm: dts: k3-am64: sync with Linux DT files Sync AM64 DT files with Linux v6.2-rc4 Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-24 09:43:25 +00:00
status = "disabled";
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14 This resyncs the dts files for all of the currently in-tree K3 platforms, along with relevant bindings, with the v5.14 Linux Kernel release. Of note are that the main-navss/mcu-navss nodes were renamed to main_navss / mcu_navss and so the u-boot.dtsi files needed to be updated to match. Tested on j721e_evm and am65x_evm. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-10 21:37:43 +00:00
mcu_gpio_intr: interrupt-controller@4210000 {
compatible = "ti,sci-intr";
reg = <0x00 0x04210000 0x00 0x200>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <5>;
ti,interrupt-ranges = <0 104 4>;
};
mcu_gpio0: gpio@4201000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&mcu_gpio_intr>;
interrupts = <30>, <31>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <23>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 79 0>;
clock-names = "gpio";
};
arm: dts: ti: k3-am64-mcu: Add pinctrl Add the definition of the pinctrl for the MCU domain. Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2022-12-05 11:10:40 +00:00
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x4084000 0x00 0x84>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
arm: dts: ti: Add Support for AM642 SoC The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:44 +00:00
};
Reference in a new issue Copy permalink