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u-boot/arch/arm/mach-rmobile/include/mach/r8a7793.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0 */
arm: rmobile: Add support R8A7793 Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-11-04 21:50:06 +00:00
/*
* arch/arm/include/asm/arch-rmobile/r8a7793.h
*
* Copyright (C) 2014 Renesas Electronics Corporation
*/
#ifndef __ASM_ARCH_R8A7793_H
#define __ASM_ARCH_R8A7793_H
#include "rcar-base.h"
/*
* R8A7793 I/O Addresses
*/
arm: rmobile: Move sh-i2c of the address defined to common header R-Car SoCs of rmobile have same IP of sh-i2c, and have same address. This moves sh-i2c of the address defined to rcar-base.h as common header of R-Car SoCs, and headers of each SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-11-06 07:03:47 +00:00
mmc: rmobile: Add SDHC support for Renesas rmobile ARM SoC This adds Renesas rmobile ARM SoC's SD/MMC host support. This drivers tested with Gose board and Koelsch board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-12-16 23:03:00 +00:00
/* SDHI */
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:41 +00:00
#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
mmc: rmobile: Add SDHC support for Renesas rmobile ARM SoC This adds Renesas rmobile ARM SoC's SD/MMC host support. This drivers tested with Gose board and Koelsch board. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-12-16 23:03:00 +00:00
arm: rmobile: Add support R8A7793 Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-11-04 21:50:06 +00:00
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
#define DBSC3_1_QOS_R3_BASE 0xE67A1300
#define DBSC3_1_QOS_R4_BASE 0xE67A1400
#define DBSC3_1_QOS_R5_BASE 0xE67A1500
#define DBSC3_1_QOS_R6_BASE 0xE67A1600
#define DBSC3_1_QOS_R7_BASE 0xE67A1700
#define DBSC3_1_QOS_R8_BASE 0xE67A1800
#define DBSC3_1_QOS_R9_BASE 0xE67A1900
#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
#define DBSC3_1_QOS_W0_BASE 0xE67A2000
#define DBSC3_1_QOS_W1_BASE 0xE67A2100
#define DBSC3_1_QOS_W2_BASE 0xE67A2200
#define DBSC3_1_QOS_W3_BASE 0xE67A2300
#define DBSC3_1_QOS_W4_BASE 0xE67A2400
#define DBSC3_1_QOS_W5_BASE 0xE67A2500
#define DBSC3_1_QOS_W6_BASE 0xE67A2600
#define DBSC3_1_QOS_W7_BASE 0xE67A2700
#define DBSC3_1_QOS_W8_BASE 0xE67A2800
#define DBSC3_1_QOS_W9_BASE 0xE67A2900
#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_1_DBADJ2 0xE67A00C8
/*
* R8A7793 I/O Product Information
*/
arm: rmobile: rcar: Add infomation of bits for module control register This adds infomation of bits for module control register. This is used to control modules on ARM R-Car SoCs. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-02 07:52:22 +00:00
/* Module stop control/status register bits */
#define MSTP0_BITS 0x00640801
#define MSTP1_BITS 0x9B6C9B5A
#define MSTP2_BITS 0x100D21FC
#define MSTP3_BITS 0xF08CD810
#define MSTP4_BITS 0x800001C4
#define MSTP5_BITS 0x44C00046
#define MSTP7_BITS 0x05BFE618
#define MSTP8_BITS 0x40C0FE85
#define MSTP9_BITS 0xFF979FFF
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
arm: rmobile: Add support R8A7793 Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-11-04 21:50:06 +00:00
#define R8A7793_CUT_ES2X 2
#define IS_R8A7793_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7793_H */
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