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u-boot/arch/mips/cpu/start.S

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
/*
* Startup Code for MIPS32 CPU-core
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*/
Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-10-26 12:34:52 +00:00
#include <asm-offsets.h>
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#include <config.h>
MIPS: use asm.h macros in mips32 start.S Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:08 +00:00
#include <asm/asm.h>
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#include <asm/regdef.h>
#include <asm/mipsregs.h>
MIPS: add support for CONFIG_SYS_INIT_SP_ADDR Support the existing config option CONFIG_SYS_INIT_SP_ADDR on MIPS. This allows to move the initial stack to other places than the beginning of RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-18 21:18:38 +00:00
#ifndef CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_SP_OFFSET)
#endif
MIPS: handle mips64 relocs in mips32 start.S In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:09 +00:00
#ifdef CONFIG_32BIT
MIPS: handle mips64 ST0_KX bit in mips32 start.S In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:10 +00:00
# define STATUS_SET 0
MIPS: handle mips64 relocs in mips32 start.S In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:09 +00:00
#endif
#ifdef CONFIG_64BIT
MIPS: handle mips64 ST0_KX bit in mips32 start.S In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:10 +00:00
# define STATUS_SET ST0_KX
MIPS: handle mips64 relocs in mips32 start.S In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:09 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
.set noreorder
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 23:37:59 +00:00
.macro init_wr sel
MTC0 zero, CP0_WATCHLO,\sel
mtc0 t1, CP0_WATCHHI,\sel
mfc0 t0, CP0_WATCHHI,\sel
bgez t0, wr_done
nop
.endm
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
.macro uhi_mips_exception
move k0, t9 # preserve t9 in k0
move k1, a0 # preserve a0 in k1
li t9, 15 # UHI exception operation
li a0, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
.endm
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
.macro setup_stack_gd
li t0, -16
PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
and sp, t1, t0 # force 16 byte alignment
PTR_SUBU \
sp, sp, GD_SIZE # reserve space for gd
and sp, sp, t0 # force 16 byte alignment
move k0, sp # save gd pointer
mips: add a option to support not reserving malloc space on initial stack The initial stack on some platforms is too small to hold a large malloc space. This patch adds a option to allow these platforms not reserving the malloc space on initial stack. These platforms should set the malloc base after DRAM is usable. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-21 07:28:33 +00:00
#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-Boot Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-24 09:45:27 +00:00
li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
PTR_SUBU \
sp, sp, t2 # reserve space for early malloc
and sp, sp, t0 # force 16 byte alignment
#endif
move fp, sp
/* Clear gd */
move t0, k0
1:
PTR_S zero, 0(t0)
mips: start.S: avoid overwriting outside gd when clearing global data in stack When setting up initial stack, global data will also be put in the stack, and being cleared. The assembler instructions for clearing gd is as follows: move t0, k0 1: PTR_S zero, 0(t0) blt t0, t1, 1b PTR_ADDIU t0, PTRSIZE t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE). [PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it will be executed before the branch operation. However the comparison for the BLT instruction is done before executing the delay slot. This means when the last word just before k1 is cleared, the loop will continue to run once. This will clear an extra word at k1, which is outside the global data. Global data is placed at the top of the stack. If the initial stack is a SRAM or locked cache, the area outside them may be inaccessible. A write operation performed in this area may cause an exception. To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT instruction. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-21 07:28:28 +00:00
PTR_ADDIU t0, PTRSIZE
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
blt t0, t1, 1b
mips: start.S: avoid overwriting outside gd when clearing global data in stack When setting up initial stack, global data will also be put in the stack, and being cleared. The assembler instructions for clearing gd is as follows: move t0, k0 1: PTR_S zero, 0(t0) blt t0, t1, 1b PTR_ADDIU t0, PTRSIZE t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE). [PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it will be executed before the branch operation. However the comparison for the BLT instruction is done before executing the delay slot. This means when the last word just before k1 is cleared, the loop will continue to run once. This will clear an extra word at k1, which is outside the global data. Global data is placed at the top of the stack. If the initial stack is a SRAM or locked cache, the area outside them may be inaccessible. A write operation performed in this area may cause an exception. To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT instruction. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-21 07:28:28 +00:00
nop
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
mips: add a option to support not reserving malloc space on initial stack The initial stack on some platforms is too small to hold a large malloc space. This patch adds a option to allow these platforms not reserving the malloc space on initial stack. These platforms should set the malloc base after DRAM is usable. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-21 07:28:33 +00:00
#if CONFIG_VAL(SYS_MALLOC_F_LEN) && \
!CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
#endif
.endm
MIPS: fix annotation of _start and relocate_code Correctly annotate _start and relocate_code as functions to produce more readable disassembly code generated by objdump. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-12-19 19:20:45 +00:00
ENTRY(_start)
Use correct spelling of "U-Boot" Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 03:30:11 +00:00
/* U-Boot entry point */
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
b reset
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 23:37:59 +00:00
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
MIPS: start.S: make boot config at offset 0x10 configurable Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-07 17:18:44 +00:00
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-27 11:22:37 +00:00
/*
MIPS: start.S: make boot config at offset 0x10 configurable Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-07 17:18:44 +00:00
* Store some board-specific boot configuration. This is used by some
* MIPS systems like Malta.
MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-07-27 11:22:37 +00:00
*/
MIPS: make inclusion of ROM exception vectors configurable This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-14 17:52:57 +00:00
.org 0x10
MIPS: start.S: make boot config at offset 0x10 configurable Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-07 17:18:44 +00:00
.word CONFIG_MIPS_BOOT_CONFIG_WORD0
.word CONFIG_MIPS_BOOT_CONFIG_WORD1
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
#endif
* Code cleanup: - remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
MIPS: make inclusion of ROM exception vectors configurable This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-14 17:52:57 +00:00
#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
/*
* Exception vector entry points. When running from ROM, an exception
* cannot be handled. Halt execution and transfer control to debugger,
* if one is attached.
*/
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x200
/* TLB refill, 32 bit task */
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
uhi_mips_exception
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x280
/* XTLB refill, 64 bit task */
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
uhi_mips_exception
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x300
/* Cache error exception */
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
uhi_mips_exception
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x380
/* General exception */
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
uhi_mips_exception
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x400
/* Catch interrupt exceptions */
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
uhi_mips_exception
MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12 21:22:12 +00:00
.org 0x480
/* EJTAG debug exception */
1: b 1b
nop
MIPS: make inclusion of ROM exception vectors configurable This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-14 17:52:57 +00:00
.org 0x500
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
reset:
MIPS: Hang if run on a secondary CPU Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 13:59:54 +00:00
#if __mips_isa_rev >= 6
mfc0 t0, CP0_CONFIG, 5
and t0, t0, MIPS_CONF5_VP
beqz t0, 1f
nop
b 2f
mfc0 t0, CP0_GLOBALNUMBER
#endif
MIPS: add initial infrastructure for Broadcom MIPS SoCs CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 22:39:20 +00:00
#ifdef CONFIG_ARCH_BMIPS
1: mfc0 t0, CP0_DIAGNOSTIC, 3
and t0, t0, (1 << 31)
#else
MIPS: Hang if run on a secondary CPU Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 13:59:54 +00:00
1: mfc0 t0, CP0_EBASE
mips: sync asm/mipsregs.h with Linux 5.7 Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 23:46:18 +00:00
and t0, t0, MIPS_EBASE_CPUNUM
MIPS: add initial infrastructure for Broadcom MIPS SoCs CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 22:39:20 +00:00
#endif
MIPS: Hang if run on a secondary CPU Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 13:59:54 +00:00
/* Hang if this isn't the first CPU in the system */
2: beqz t0, 4f
nop
3: wait
b 3b
nop
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 23:37:59 +00:00
/* Init CP0 Status */
4: mfc0 t0, CP0_STATUS
and t0, ST0_IMPL
or t0, ST0_BEV | ST0_ERL | STATUS_SET
mtc0 t0, CP0_STATUS
/*
* Check whether CP0 Config1 is implemented. If not continue
* with legacy Watch register initialization.
*/
mfc0 t0, CP0_CONFIG
bgez t0, wr_legacy
nop
/*
* Check WR bit in CP0 Config1 to determine if Watch registers
* are implemented.
*/
mfc0 t0, CP0_CONFIG, 1
andi t0, (1 << 3)
beqz t0, wr_done
nop
/* Clear Watch Status bits and disable watch exceptions */
li t1, 0x7 # Clear I, R and W conditions
init_wr 0
init_wr 1
init_wr 2
init_wr 3
init_wr 4
init_wr 5
init_wr 6
init_wr 7
b wr_done
nop
wr_legacy:
MTC0 zero, CP0_WATCHLO
MIPS: start.S: fix and optimize instructions Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-09 21:24:47 +00:00
mtc0 zero, CP0_WATCHHI
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 23:37:59 +00:00
wr_done:
/* Clear WP, IV and SW interrupts */
[MIPS] Initialize CP0 Cause before setting up CP0 Status register Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-03-25 12:30:07 +00:00
mtc0 zero, CP0_CAUSE
MIPS: fix iand optimize setup of CP0 registers Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 23:37:59 +00:00
/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
mtc0 zero, CP0_COMPARE
mips: add config options for generic cache setup code Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:57 +00:00
#ifdef CONFIG_MIPS_CACHE_DISABLE
mips: refactor disabling of caches Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:56 +00:00
/* Disable caches */
PTR_LA t9, mips_cache_disable
jalr t9
nop
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: Map CM Global Control Registers Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:53 +00:00
#ifdef CONFIG_MIPS_CM
PTR_LA t9, mips_cm_map
jalr t9
nop
#endif
MIPS: add possibility to setup initial stack and global data in SRAM This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-06-04 14:13:21 +00:00
#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
mips: add an option to support initialize SRAM for initial stack Currently CONFIG_MIPS_INIT_STACK_IN_SRAM assumes the memory space for the initial stack can be used directly. However on some platform the SRAM needs initialization, e.g. lock cache. This patch adds an option to allow a new function mips_sram_init() being called before setup_stack_gd. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-21 07:28:27 +00:00
#ifdef CONFIG_MIPS_SRAM_INIT
/* Initialize the SRAM first */
PTR_LA t9, mips_sram_init
jalr t9
nop
#endif
MIPS: add possibility to setup initial stack and global data in SRAM This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-06-04 14:13:21 +00:00
/* Set up initial stack and global data */
setup_stack_gd
MIPS: call debug_uart_init right before board_init_f All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-04-24 17:03:34 +00:00
# ifdef CONFIG_DEBUG_UART
/* Earliest point to set up debug uart */
PTR_LA t9, debug_uart_init
jalr t9
nop
# endif
MIPS: add possibility to setup initial stack and global data in SRAM This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-06-04 14:13:21 +00:00
#endif
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
MIPS: If we don't need DDR for cache init, init cache first On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:51 +00:00
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Initialize any external memory */
MIPS: use asm.h macros in mips32 start.S Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:08 +00:00
PTR_LA t9, lowlevel_init
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
jalr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
MIPS: If we don't need DDR for cache init, init cache first On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:51 +00:00
# endif
mips: add config options for generic cache setup code Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:57 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
mips: add config options for generic cache setup code Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:57 +00:00
#ifdef CONFIG_MIPS_CACHE_SETUP
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
/* Initialize caches... */
MIPS: use asm.h macros in mips32 start.S Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:08 +00:00
PTR_LA t9, mips_cache_reset
[MIPS] MIPS 4K core: Coding style cleanups No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2007-10-27 06:27:06 +00:00
jalr t9
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
nop
mips: add config options for generic cache setup code Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:57 +00:00
#endif
MIPS: If we don't need DDR for cache init, init cache first On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:51 +00:00
mips: add config options for generic cache setup code Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-11 22:45:57 +00:00
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
MIPS: If we don't need DDR for cache init, init cache first On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 10:18:51 +00:00
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
jalr t9
nop
# endif
MIPS: Coding style cleanups on common assembly files Fix style issues and alignments globally. No logical changes. - Replace C comments with AS line comments where possible - Use ifndef where possible, rather than if !defined for simplicity - An instruction executed in a delay slot is now indicated by a leading space, not by C comment Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
2011-05-06 15:18:13 +00:00
#endif
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: add possibility to setup initial stack and global data in SRAM This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-06-04 14:13:21 +00:00
#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
MIPS: factor out code for initial stack and global data Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-25 16:36:38 +00:00
/* Set up initial stack and global data */
setup_stack_gd
MIPS: call debug_uart_init right before board_init_f All MIPS boards that support debug uart are calling debug_uart_init right at the beginning of board_early_init_f. Instead of doing that, let's provide a generic call to debug_uart_init right before the call to board_init_f if debug uart is enabled for boards without stack in SRAM. On the other hand, boards with stack in SRAM can call earlier (right before low level init). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2017-04-24 17:03:34 +00:00
# ifdef CONFIG_DEBUG_UART
/* Earliest point to set up debug uart */
PTR_LA t9, debug_uart_init
jalr t9
nop
# endif
MIPS: add possibility to setup initial stack and global data in SRAM This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-06-04 14:13:21 +00:00
#endif
MIPS: start.S: fix and optimize instructions Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-09 21:24:47 +00:00
MIPS: initialize board_init_f() argument to zero. Argument boot_flags of board_init_f() should be set to 0 as $a0 may be utilized in lowlevel_init() or mips_cache_reset() or previous stage boot-loader. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-21 14:32:51 +00:00
move a0, zero # a0 <-- boot_flags = 0
MIPS: use asm.h macros in mips32 start.S Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-01-29 10:04:08 +00:00
PTR_LA t9, board_init_f
MIPS: fix ROM exception vectors When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-07 18:39:58 +00:00
Use jr as register jump instruction Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage at all. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-04-17 14:35:13 +00:00
jr t9
MIPS: fix setup of initial stack frame To get correct stack walking and backtrace functionality in gdb, registers fp and ra should be initialized before calling board_init_f or board_init_r. Thus allocating stack space and zeroing it as it is currently done in board.c becomes obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-11-20 22:55:32 +00:00
move ra, zero
* Add support for MIPS32 4Kc CPUs * Add support for INCA-IP Board
2003-03-27 12:09:35 +00:00
MIPS: fix annotation of _start and relocate_code Correctly annotate _start and relocate_code as functions to produce more readable disassembly code generated by objdump. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-12-19 19:20:45 +00:00
END(_start)
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