2011-07-07 04:29:15 +00:00
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/*
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2012-04-18 19:39:53 +00:00
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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2011-07-07 04:29:15 +00:00
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-07-07 04:29:15 +00:00
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*/
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/*
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* P2041 RDB board configuration file
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2012-08-14 10:14:51 +00:00
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* Also supports P2040 RDB
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2011-07-07 04:29:15 +00:00
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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2014-03-11 02:05:16 +00:00
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
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2011-07-07 04:29:15 +00:00
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#endif
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powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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2012-08-09 05:09:59 +00:00
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/* Set 1M boot space */
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powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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2012-08-09 05:09:59 +00:00
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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2011-07-07 04:29:15 +00:00
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/* High Level Configuration Options */
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
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#define CONFIG_MP /* support multiple processors */
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#ifndef CONFIG_SYS_TEXT_BASE
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2014-01-14 06:04:26 +00:00
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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2011-07-07 04:29:15 +00:00
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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2016-12-28 16:43:45 +00:00
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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2016-05-03 23:52:49 +00:00
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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2011-07-07 04:29:15 +00:00
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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2013-05-07 08:30:46 +00:00
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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2011-10-14 18:28:52 +00:00
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#define CONFIG_SYS_DPAA_RMAN /* RMan */
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2011-07-07 04:29:15 +00:00
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#define CONFIG_ENV_OVERWRITE
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2017-02-11 13:43:54 +00:00
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#ifndef CONFIG_MTD_NOR_FLASH
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2011-07-07 04:29:15 +00:00
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#else
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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2012-06-28 23:35:34 +00:00
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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2011-07-07 04:29:15 +00:00
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#endif
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#if defined(CONFIG_SPIFLASH)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 10000000
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#elif defined(CONFIG_SDCARD)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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2012-01-11 09:20:50 +00:00
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#define CONFIG_FSL_FIXED_MMC_LOCATION
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2011-07-07 04:29:15 +00:00
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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2014-01-14 06:04:26 +00:00
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#define CONFIG_ENV_OFFSET (512 * 1658)
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2012-02-28 23:28:40 +00:00
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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2014-01-14 06:04:26 +00:00
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#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
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powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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2012-08-09 05:09:59 +00:00
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#define CONFIG_ENV_ADDR 0xffe20000
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#define CONFIG_ENV_SIZE 0x2000
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2012-06-28 23:35:34 +00:00
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#elif defined(CONFIG_ENV_IS_NOWHERE)
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2012-08-09 05:09:59 +00:00
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#define CONFIG_ENV_SIZE 0x2000
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2011-07-07 04:29:15 +00:00
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
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- CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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2011-09-13 09:55:11 +00:00
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
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2011-07-07 04:29:15 +00:00
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_CACHE_STASHING
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2011-07-21 22:03:54 +00:00
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#define CONFIG_BACKSIDE_L2_CACHE
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
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2011-07-07 04:29:15 +00:00
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ENABLE_36BIT_PHYS
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
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#endif
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
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CONFIG_RAMBOOT_TEXT_BASE)
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#else
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#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
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#endif
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#define CONFIG_SYS_L3_SIZE (1024 << 10)
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#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define SPD_EEPROM_ADDRESS 0x52
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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/*
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* Local Bus Definitions
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*/
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/* Set the local bus clock 1/8 of platform clock */
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#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
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2012-10-26 16:40:15 +00:00
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/*
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* This board doesn't have a promjet connector.
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* However, it uses commone corenet board LAW and TLB.
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* It is necessary to use the same start address with proper offset.
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2012-10-26 16:40:15 +00:00
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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2011-07-07 04:29:15 +00:00
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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2012-02-28 23:28:07 +00:00
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#define CONFIG_SYS_FLASH_BR_PRELIM \
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2012-10-26 16:40:15 +00:00
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(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
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BR_PS_16 | BR_V)
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2012-02-28 23:28:07 +00:00
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#define CONFIG_SYS_FLASH_OR_PRELIM \
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((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
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| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
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2011-07-07 04:29:15 +00:00
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#define CONFIG_FSL_CPLD
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#define CPLD_BASE 0xffdf0000 /* CPLD registers */
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#ifdef CONFIG_PHYS_64BIT
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#define CPLD_BASE_PHYS 0xfffdf0000ull
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#else
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#define CPLD_BASE_PHYS CPLD_BASE
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#endif
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|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
|
|
|
|
|
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
|
|
|
|
|
|
|
|
|
#define PIXIS_LBMAP_SWITCH 7
|
|
|
|
|
#define PIXIS_LBMAP_MASK 0xf0
|
|
|
|
|
#define PIXIS_LBMAP_SHIFT 4
|
|
|
|
|
#define PIXIS_LBMAP_ALTBANK 0x40
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FLASH_QUIET_TEST
|
|
|
|
|
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
|
|
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
|
|
|
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
|
|
|
|
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_RAMBOOT_PBL)
|
|
|
|
|
#define CONFIG_SYS_RAMBOOT
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-02-28 23:28:07 +00:00
|
|
|
#define CONFIG_NAND_FSL_ELBC
|
|
|
|
|
/* Nand Flash */
|
|
|
|
|
#ifdef CONFIG_NAND_FSL_ELBC
|
|
|
|
|
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
|
|
|
|
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
|
|
|
#define CONFIG_CMD_NAND
|
|
|
|
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
|
|
|
|
|
|
|
|
|
/* NAND flash config */
|
|
|
|
|
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
|
|
|
|
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
|
|
|
|
| BR_PS_8 /* Port Size = 8 bit */ \
|
|
|
|
|
| BR_MS_FCM /* MSEL = FCM */ \
|
|
|
|
|
| BR_V) /* valid */
|
|
|
|
|
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
|
|
|
|
| OR_FCM_PGS /* Large Page*/ \
|
|
|
|
|
| OR_FCM_CSCT \
|
|
|
|
|
| OR_FCM_CST \
|
|
|
|
|
| OR_FCM_CHT \
|
|
|
|
|
| OR_FCM_SCY_1 \
|
|
|
|
|
| OR_FCM_TRLX \
|
|
|
|
|
| OR_FCM_EHTR)
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_NAND
|
|
|
|
|
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
|
|
|
|
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
|
|
|
|
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
|
|
|
|
|
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
|
|
|
|
|
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
|
|
|
|
|
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
|
|
|
|
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
|
|
|
|
#endif
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
|
|
|
|
|
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
|
|
|
|
|
#endif /* CONFIG_NAND_FSL_ELBC */
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
|
|
|
|
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
2012-10-26 16:40:15 +00:00
|
|
|
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
|
|
|
|
#define CONFIG_MISC_INIT_R
|
|
|
|
|
|
|
|
|
|
#define CONFIG_HWCONFIG
|
|
|
|
|
|
|
|
|
|
/* define to use L1 as initial stack */
|
|
|
|
|
#define CONFIG_L1_INIT_RAM
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_LOCK
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
|
|
|
|
|
/* The assembler doesn't like typecast */
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
|
|
|
|
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
|
|
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
|
|
|
|
GENERATED_GBL_DATA_SIZE)
|
|
|
|
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
|
|
|
|
2014-03-31 10:01:48 +00:00
|
|
|
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
2011-07-07 04:29:15 +00:00
|
|
|
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
|
|
|
|
|
|
|
|
|
/* Serial Port - controlled on board with jumper J8
|
|
|
|
|
* open - index 2
|
|
|
|
|
* shorted - index 1
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_CONS_INDEX 1
|
|
|
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
|
|
|
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
|
|
|
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
|
|
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
|
|
|
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
|
|
|
|
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
|
|
|
|
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
|
|
|
|
|
|
|
|
|
/* I2C */
|
2012-10-24 11:48:22 +00:00
|
|
|
#define CONFIG_SYS_I2C
|
|
|
|
|
#define CONFIG_SYS_I2C_FSL
|
|
|
|
|
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
|
|
|
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
2013-09-10 08:15:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
2012-10-24 11:48:22 +00:00
|
|
|
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
|
|
|
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
2013-09-10 08:15:07 +00:00
|
|
|
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RapidIO
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
|
|
|
|
|
|
2012-08-09 05:09:59 +00:00
|
|
|
/*
|
|
|
|
|
* for slave u-boot IMAGE instored in master memory space,
|
|
|
|
|
* PHYS must be aligned based on the SIZE
|
|
|
|
|
*/
|
2014-05-15 06:30:34 +00:00
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
|
|
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
|
|
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
|
|
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
|
2012-08-09 05:09:59 +00:00
|
|
|
/*
|
|
|
|
|
* for slave UCODE and ENV instored in master memory space,
|
|
|
|
|
* PHYS must be aligned based on the SIZE
|
|
|
|
|
*/
|
2014-05-15 06:30:34 +00:00
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
|
2012-08-09 05:10:02 +00:00
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
|
|
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
|
2012-08-09 05:09:59 +00:00
|
|
|
|
|
|
|
|
/* slave core release by master*/
|
2012-08-09 05:10:02 +00:00
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
|
|
|
|
|
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
|
2012-08-09 05:09:59 +00:00
|
|
|
|
|
|
|
|
/*
|
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
* SRIO_PCIE_BOOT - SLAVE
|
2012-08-09 05:09:59 +00:00
|
|
|
*/
|
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
|
|
|
|
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
|
|
|
|
|
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
|
|
|
|
|
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
|
2012-08-09 05:09:59 +00:00
|
|
|
#endif
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
/*
|
|
|
|
|
* eSPI - Enhanced SPI
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
|
|
|
|
#define CONFIG_SF_DEFAULT_MODE 0
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* General PCI
|
|
|
|
|
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
|
|
|
|
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
|
|
|
|
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
|
|
|
|
|
|
|
|
|
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
|
|
|
|
|
|
|
|
|
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
|
|
|
|
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
|
|
|
|
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
|
|
|
|
|
|
|
|
|
/* Qman/Bman */
|
|
|
|
|
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
|
|
|
|
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
|
|
|
|
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
2014-12-08 19:54:01 +00:00
|
|
|
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
|
|
|
|
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
|
|
|
|
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
|
|
|
|
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
|
|
|
|
CONFIG_SYS_BMAN_CENA_SIZE)
|
|
|
|
|
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
2011-07-07 04:29:15 +00:00
|
|
|
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
|
|
|
|
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
|
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
|
|
|
|
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
|
|
|
|
#endif
|
|
|
|
|
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
2014-12-08 19:54:01 +00:00
|
|
|
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
|
|
|
|
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
|
|
|
|
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
|
|
|
|
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
|
|
|
|
CONFIG_SYS_QMAN_CENA_SIZE)
|
|
|
|
|
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#define CONFIG_SYS_DPAA_FMAN
|
|
|
|
|
#define CONFIG_SYS_DPAA_PME
|
|
|
|
|
/* Default address of microcode for the Linux Fman driver */
|
|
|
|
|
#if defined(CONFIG_SPIFLASH)
|
|
|
|
|
/*
|
|
|
|
|
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
|
|
|
|
* env, so we got 0x110000.
|
|
|
|
|
*/
|
2011-11-22 15:21:25 +00:00
|
|
|
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
2014-03-21 08:21:44 +00:00
|
|
|
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
|
2011-07-07 04:29:15 +00:00
|
|
|
#elif defined(CONFIG_SDCARD)
|
|
|
|
|
/*
|
|
|
|
|
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
2014-01-14 06:04:26 +00:00
|
|
|
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
|
|
|
|
|
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
|
2011-07-07 04:29:15 +00:00
|
|
|
*/
|
2011-11-22 15:21:25 +00:00
|
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
2014-03-21 08:21:44 +00:00
|
|
|
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
|
2011-07-07 04:29:15 +00:00
|
|
|
#elif defined(CONFIG_NAND)
|
2011-11-22 15:21:25 +00:00
|
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
2014-03-21 08:21:44 +00:00
|
|
|
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
|
2012-08-09 05:09:59 +00:00
|
|
|
/*
|
|
|
|
|
* Slave has no ucode locally, it can fetch this from remote. When implementing
|
|
|
|
|
* in two corenet boards, slave's ucode could be stored in master's memory
|
|
|
|
|
* space, the address can be mapped from slave TLB->slave LAW->
|
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
* slave SRIO or PCIE outbound window->master inbound window->
|
|
|
|
|
* master LAW->the ucode address in master's memory space.
|
2012-08-09 05:09:59 +00:00
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
|
2014-03-21 08:21:44 +00:00
|
|
|
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
|
2011-07-07 04:29:15 +00:00
|
|
|
#else
|
2011-11-22 15:21:25 +00:00
|
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
2014-03-21 08:21:44 +00:00
|
|
|
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
2011-11-22 15:21:25 +00:00
|
|
|
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
|
|
|
|
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
|
|
|
|
#define CONFIG_FMAN_ENET
|
2011-07-19 08:20:13 +00:00
|
|
|
#define CONFIG_PHYLIB_10G
|
|
|
|
|
#define CONFIG_PHY_VITESSE
|
|
|
|
|
#define CONFIG_PHY_TERANETICS
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
2013-05-30 07:06:12 +00:00
|
|
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
|
2011-07-27 01:55:51 +00:00
|
|
|
/* SATA */
|
2012-11-26 00:05:38 +00:00
|
|
|
#define CONFIG_FSL_SATA_V2
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_SATA_V2
|
2011-07-27 01:55:51 +00:00
|
|
|
#define CONFIG_FSL_SATA
|
2011-11-21 23:10:22 +00:00
|
|
|
#define CONFIG_LIBATA
|
2011-07-27 01:55:51 +00:00
|
|
|
|
|
|
|
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
|
|
|
|
#define CONFIG_SATA1
|
|
|
|
|
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
|
|
|
|
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
|
|
|
|
#define CONFIG_SATA2
|
|
|
|
|
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
|
|
|
|
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
|
|
|
|
|
|
|
|
|
#define CONFIG_LBA48
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
#ifdef CONFIG_FMAN_ENET
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
|
|
|
|
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
|
|
|
|
|
2011-07-19 08:20:13 +00:00
|
|
|
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
#define CONFIG_SYS_TBIPA_VALUE 8
|
|
|
|
|
#define CONFIG_MII /* MII PHY management */
|
|
|
|
|
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
|
|
|
|
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Environment
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
|
|
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Command line configuration.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
#define CONFIG_CMD_PCI
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* USB
|
|
|
|
|
*/
|
2012-04-18 19:39:53 +00:00
|
|
|
#define CONFIG_HAS_FSL_DR_USB
|
|
|
|
|
#define CONFIG_HAS_FSL_MPH_USB
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
|
2011-07-07 04:29:15 +00:00
|
|
|
#define CONFIG_USB_EHCI_FSL
|
|
|
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
2012-04-18 19:39:53 +00:00
|
|
|
#endif
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
#ifdef CONFIG_MMC
|
|
|
|
|
#define CONFIG_FSL_ESDHC
|
|
|
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
|
|
|
|
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
|
|
|
|
|
#endif
|
2014-10-15 06:05:31 +00:00
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
/*
|
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
|
|
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
|
|
|
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
|
|
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
|
|
|
#ifdef CONFIG_CMD_KGDB
|
|
|
|
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
|
|
|
#endif
|
|
|
|
|
/* Print Buffer Size */
|
|
|
|
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
|
|
|
|
sizeof(CONFIG_SYS_PROMPT)+16)
|
|
|
|
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
|
|
|
/* Boot Argument Buffer Size */
|
|
|
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For booting Linux, the board info and command line data
|
|
|
|
|
* have to be in the first 64 MB of memory, since this is
|
|
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
|
|
|
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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2011-10-13 13:03:47 +00:00
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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2011-10-13 13:03:48 +00:00
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#define CONFIG_BOOTFILE "uImage"
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2011-07-07 04:29:15 +00:00
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#define CONFIG_UBOOTPATH u-boot.bin
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define __USB_PHY_TYPE utmi
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
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"bank_intlv=cs0_cs1\0" \
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"netdev=eth0\0" \
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2012-09-23 15:41:24 +00:00
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"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
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"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
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2011-07-07 04:29:15 +00:00
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"tftpflash=tftpboot $loadaddr $uboot && " \
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"protect off $ubootaddr +$filesize && " \
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"erase $ubootaddr +$filesize && " \
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"cp.b $loadaddr $ubootaddr $filesize && " \
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"protect on $ubootaddr +$filesize && " \
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"cmp.b $loadaddr $ubootaddr $filesize\0" \
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"consoledev=ttyS0\0" \
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2012-09-23 15:41:24 +00:00
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"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
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2011-07-07 04:29:15 +00:00
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"usb_dr_mode=host\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
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2016-07-19 22:52:06 +00:00
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"fdtaddr=1e00000\0" \
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2011-07-07 04:29:15 +00:00
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"fdtfile=p2041rdb/p2041rdb.dtb\0" \
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2014-05-15 00:33:45 +00:00
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"bdev=sda3\0"
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2011-07-07 04:29:15 +00:00
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
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#include <asm/fsl_secure_boot.h>
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#endif /* __CONFIG_H */
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