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drivers: cosmetic: Convert SPDX license tags to Linux Kernel style Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-26 07:02:52 +00:00
# SPDX-License-Identifier: GPL-2.0+
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
#
# Copyright (c) 2015 Google, Inc
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
clk: Add fixed-factor clock driver This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-25 08:14:55 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
clk: add clk-gate support Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 07:01:34 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-06-24 13:50:45 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
clk: add composite clk support Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 07:01:54 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
clock: add Tegra186 clock driver In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 17:28:24 +00:00
clk: sifive: Factor-out PLL library as separate module To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-25 06:31:02 +00:00
obj-y += analogbits/
clk: imx: add clk driver for i.MX8QXP Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2018-10-18 12:28:30 +00:00
obj-y += imx/
clk: starfive: Add StarFive JH7110 clock driver Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 03:42:13 +00:00
obj-$(CONFIG_CLK_JH7110) += starfive/
clock: add Tegra186 clock driver In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 17:28:24 +00:00
obj-y += tegra/
clk: ti: add mux clock driver The driver manages a register-mapped multiplexer with multiple input clock signals or parents, one of which can be selected as output. It uses routines provided by the common clock framework (ccf). The code is based on the drivers/clk/ti/mux.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/mux.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-12-29 23:06:32 +00:00
obj-y += ti/
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
clk: MediaTek: add clock driver for MT7629 SoC. This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-15 02:07:54 +00:00
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
clk: create meson directory and move related drivers In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-02-10 13:54:30 +00:00
obj-$(CONFIG_ARCH_MESON) += meson/
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
clk: nuvoton: Add support for NPCM750 Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-04-19 05:32:20 +00:00
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
clk: socfpga: Add initial Arria10 clock driver Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-31 15:58:07 +00:00
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
clk: Add directory for STM32 clock drivers Add a directory in drivers/clk to regroup the clock drivers for all STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or CONFIG_ARCH_STM32MP (MPUs with cortex A). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Acked-by: Sean Anderson <seanga2@gmail.com> Change-Id: I955af307963f732167396f0157a30cf2fc91f150
2022-05-19 15:56:45 +00:00
obj-$(CONFIG_ARCH_STM32) += stm32/
obj-$(CONFIG_ARCH_STM32MP) += stm32/
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
clk: at91: Add clock driver The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-20 09:55:12 +00:00
obj-$(CONFIG_CLK_AT91) += at91/
dm: clk: add BCM6345 clock driver This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-07 18:13:01 +00:00
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
clk: boston: Providea simple driver for Boston board clocks Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-08 06:47:38 +00:00
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_EXYNOS) += exynos/
ARC: clk: introduce HSDK CGU clock driver Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-10 18:20:08 +00:00
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
k210: use the board vendor name rather than the marketing name "kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-01 10:35:39 +00:00
obj-$(CONFIG_CLK_K210) += clk_k210.o
clk: Add MPC83xx clock driver Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:36 +00:00
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
clk: Add Microchip PolarFire SoC clock driver Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2021-01-15 02:50:38 +00:00
obj-$(CONFIG_CLK_MPFS) += microchip/
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_CLK_MVEBU) += mvebu/
clk: clk_octeon: Add simple MIPS Octeon clock driver This patch adds a simple clock driver for the Marvell Octeon MIPS SoC family. Its for IO clock rate passing via DT in some of the Octeon driver, like I2C. So that we don't need to use the non-mainline API octeon_get_io_clock(). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Lukasz Majewski <lukma@denx.de>
2020-07-30 11:56:16 +00:00
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
clk: Add Actions Semi OWL clock support This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-14 18:08:35 +00:00
obj-$(CONFIG_CLK_OWL) += owl/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_RENESAS) += renesas/
clk: scmi: Add Kconfig option for SPL Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options enabled and SPL_FIRMWARE disabled result in the following error. drivers/clk/clk_scmi.o: in function `scmi_clk_gate': drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_probe': drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make: *** [Makefile:2043: spl/u-boot-spl] Error 2 Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-17 19:07:18 +00:00
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
clk: Add SiFive FU540 PRCI clock driver Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-25 08:14:49 +00:00
obj-$(CONFIG_CLK_SIFIVE) += sifive/
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
clk: Add support for Arm's Versatile Express OSC clock generators The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-09-17 16:50:00 +00:00
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
clk: Rename ICS8N3QV01 to CLK_ICS8N3QV01 This driver was missing a clock prefix. Add one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-4-seanga2@gmail.com
2021-12-15 16:36:20 +00:00
obj-$(CONFIG_CLK_ICS8N3QV01) += ics8n3qv01.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
clk: Alphabetize Makefile This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com
2021-12-15 16:36:18 +00:00
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
clk: Makefile: Sort entries alphabetically The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:54 +00:00
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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