Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-18 10:48:51 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/include/asm/arch-tegra20/pinmux.h

239 lines
4.3 KiB
C
Raw Normal View History

arm: Tegra2: Add basic NVIDIA Tegra2 SoC support Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-01-27 10:58:05 +00:00
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-08 07:37:19 +00:00
* SPDX-License-Identifier: GPL-2.0+
arm: Tegra2: Add basic NVIDIA Tegra2 SoC support Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-01-27 10:58:05 +00:00
*/
ARM: tegra: pinctrl: remove duplication Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:54 +00:00
#ifndef _TEGRA20_PINMUX_H_
#define _TEGRA20_PINMUX_H_
arm: Tegra2: Add basic NVIDIA Tegra2 SoC support Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-01-27 10:58:05 +00:00
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
/*
* Pin groups which we adjust. There are three basic attributes of each pin
* group which use this enum:
*
* - function
* - pullup / pulldown
* - tristate or normal
*/
tegra2: Rename PIN_ to PINGRP_ The pin groupings are better named PINGRP, since on Tegra2 they refer to multiple pins. Sorry about this, but better to get it right now when there is only a small amount of code affected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:05 +00:00
enum pmux_pingrp {
Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
2011-08-30 06:23:14 +00:00
/* APB_MISC_PP_TRISTATE_REG_A_0 */
ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:58 +00:00
PMUX_PINGRP_ATA,
PMUX_PINGRP_ATB,
PMUX_PINGRP_ATC,
PMUX_PINGRP_ATD,
PMUX_PINGRP_CDEV1,
PMUX_PINGRP_CDEV2,
PMUX_PINGRP_CSUS,
PMUX_PINGRP_DAP1,
PMUX_PINGRP_DAP2,
PMUX_PINGRP_DAP3,
PMUX_PINGRP_DAP4,
PMUX_PINGRP_DTA,
PMUX_PINGRP_DTB,
PMUX_PINGRP_DTC,
PMUX_PINGRP_DTD,
PMUX_PINGRP_DTE,
PMUX_PINGRP_GPU,
PMUX_PINGRP_GPV,
PMUX_PINGRP_I2CP,
PMUX_PINGRP_IRTX,
PMUX_PINGRP_IRRX,
PMUX_PINGRP_KBCB,
PMUX_PINGRP_KBCA,
PMUX_PINGRP_PMC,
PMUX_PINGRP_PTA,
PMUX_PINGRP_RM,
PMUX_PINGRP_KBCE,
PMUX_PINGRP_KBCF,
PMUX_PINGRP_GMA,
PMUX_PINGRP_GMC,
PMUX_PINGRP_SDIO1,
PMUX_PINGRP_OWC,
Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
2011-08-30 06:23:14 +00:00
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:58 +00:00
PMUX_PINGRP_GME,
PMUX_PINGRP_SDC,
PMUX_PINGRP_SDD,
PMUX_PINGRP_RESERVED0,
PMUX_PINGRP_SLXA,
PMUX_PINGRP_SLXC,
PMUX_PINGRP_SLXD,
PMUX_PINGRP_SLXK,
PMUX_PINGRP_SPDI,
PMUX_PINGRP_SPDO,
PMUX_PINGRP_SPIA,
PMUX_PINGRP_SPIB,
PMUX_PINGRP_SPIC,
PMUX_PINGRP_SPID,
PMUX_PINGRP_SPIE,
PMUX_PINGRP_SPIF,
PMUX_PINGRP_SPIG,
PMUX_PINGRP_SPIH,
PMUX_PINGRP_UAA,
PMUX_PINGRP_UAB,
PMUX_PINGRP_UAC,
PMUX_PINGRP_UAD,
PMUX_PINGRP_UCA,
PMUX_PINGRP_UCB,
PMUX_PINGRP_RESERVED1,
PMUX_PINGRP_ATE,
PMUX_PINGRP_KBCC,
PMUX_PINGRP_RESERVED2,
PMUX_PINGRP_RESERVED3,
PMUX_PINGRP_GMB,
PMUX_PINGRP_GMD,
PMUX_PINGRP_DDC,
Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
2011-08-30 06:23:14 +00:00
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:58 +00:00
PMUX_PINGRP_LD0,
PMUX_PINGRP_LD1,
PMUX_PINGRP_LD2,
PMUX_PINGRP_LD3,
PMUX_PINGRP_LD4,
PMUX_PINGRP_LD5,
PMUX_PINGRP_LD6,
PMUX_PINGRP_LD7,
PMUX_PINGRP_LD8,
PMUX_PINGRP_LD9,
PMUX_PINGRP_LD10,
PMUX_PINGRP_LD11,
PMUX_PINGRP_LD12,
PMUX_PINGRP_LD13,
PMUX_PINGRP_LD14,
PMUX_PINGRP_LD15,
PMUX_PINGRP_LD16,
PMUX_PINGRP_LD17,
PMUX_PINGRP_LHP0,
PMUX_PINGRP_LHP1,
PMUX_PINGRP_LHP2,
PMUX_PINGRP_LVP0,
PMUX_PINGRP_LVP1,
PMUX_PINGRP_HDINT,
PMUX_PINGRP_LM0,
PMUX_PINGRP_LM1,
PMUX_PINGRP_LVS,
PMUX_PINGRP_LSC0,
PMUX_PINGRP_LSC1,
PMUX_PINGRP_LSCK,
PMUX_PINGRP_LDC,
PMUX_PINGRP_LCSN,
Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
2011-08-30 06:23:14 +00:00
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:58 +00:00
PMUX_PINGRP_LSPI,
PMUX_PINGRP_LSDA,
PMUX_PINGRP_LSDI,
PMUX_PINGRP_LPW0,
PMUX_PINGRP_LPW1,
PMUX_PINGRP_LPW2,
PMUX_PINGRP_LDI,
PMUX_PINGRP_LHS,
PMUX_PINGRP_LPP,
PMUX_PINGRP_RESERVED4,
PMUX_PINGRP_KBCD,
PMUX_PINGRP_GPU7,
PMUX_PINGRP_DTF,
PMUX_PINGRP_UDA,
PMUX_PINGRP_CRTP,
PMUX_PINGRP_SDB,
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
/* these pin groups only have pullup and pull down control */
ARM: tegra: Tegra20 pinmux cleanup This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:58 +00:00
PMUX_PINGRP_CK32,
PMUX_PINGRP_DDRC,
PMUX_PINGRP_PMCA,
PMUX_PINGRP_PMCB,
PMUX_PINGRP_PMCC,
PMUX_PINGRP_PMCD,
PMUX_PINGRP_PMCE,
PMUX_PINGRP_XM2C,
PMUX_PINGRP_XM2D,
ARM: tegra: pinmux naming consistency fixes Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:56 +00:00
PMUX_PINGRP_COUNT,
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
};
/*
* Functions which can be assigned to each of the pin groups. The values here
* bear no relation to the values programmed into pinmux registers and are
* purely a convenience. The translation is done through a table search.
*/
enum pmux_func {
ARM: tegra: allow pinmux mux option not to be set by init tables Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change the mux option in HW. For pins that will be used as GPIOs, the mux option is irrelevant, so we simply don't want to define any mux option in the pinmux initialization table. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-04-22 20:37:52 +00:00
PMUX_FUNC_DEFAULT,
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
PMUX_FUNC_AHB_CLK,
PMUX_FUNC_APB_CLK,
PMUX_FUNC_AUDIO_SYNC,
PMUX_FUNC_CRT,
PMUX_FUNC_DAP1,
PMUX_FUNC_DAP2,
PMUX_FUNC_DAP3,
PMUX_FUNC_DAP4,
PMUX_FUNC_DAP5,
PMUX_FUNC_DISPA,
PMUX_FUNC_DISPB,
PMUX_FUNC_EMC_TEST0_DLL,
PMUX_FUNC_EMC_TEST1_DLL,
PMUX_FUNC_GMI,
PMUX_FUNC_GMI_INT,
PMUX_FUNC_HDMI,
PMUX_FUNC_I2C,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_IDE,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
PMUX_FUNC_OSC,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
PMUX_FUNC_PLLA_OUT,
PMUX_FUNC_PLLC_OUT1,
PMUX_FUNC_PLLM_OUT1,
PMUX_FUNC_PLLP_OUT2,
PMUX_FUNC_PLLP_OUT3,
PMUX_FUNC_PLLP_OUT4,
PMUX_FUNC_PWM,
PMUX_FUNC_PWR_INTR,
PMUX_FUNC_PWR_ON,
PMUX_FUNC_RTCK,
PMUX_FUNC_SDIO1,
PMUX_FUNC_SDIO2,
PMUX_FUNC_SDIO3,
PMUX_FUNC_SDIO4,
PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
PMUX_FUNC_TRACE,
PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
ARM: tegra: pack pinmux data tables tighter Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 21:58:03 +00:00
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
PMUX_FUNC_COUNT,
Tegra2: Add additional pin multiplexing features This adds an enum for each pin and some functions for changing the pin muxing setup. Signed-off-by: Simon Glass <sjg@chromium.org>
2011-08-30 06:23:14 +00:00
};
ARM: tegra: pinctrl: remove duplication Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:54 +00:00
#include <asm/arch-tegra/pinmux.h>
tegra2: Add more pinmux functions This adds support for changing pinmux functions of pin groups. This is done by defining a PMUX_FUNC_... enum which can be used to select the function for each group using pinmux_set_func(). It is also possible to enable pullup/pulldown, and the existing tristate functionality is retained. Also provided is a means of configuring a list of pingroups by providing a configuration table to pinmux_config_table(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
2011-09-21 12:40:06 +00:00
ARM: tegra: pinctrl: remove duplication Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-03-21 18:28:54 +00:00
#endif /* _TEGRA20_PINMUX_H_ */
Reference in a new issue Copy permalink