u-boot/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * NXP LS1028A-QDS device tree fragment for RCW 6xxx
 *
 * Copyright 2019-2021 NXP
 */

/*
 * This setup is using SCH-30842 cards with AQR112 PHY.
 */
&slot1 {
	#include "fsl-sch-30842.dtsi"
};

&enetc0 {
	status = "okay";
	phy-mode = "sgmii-2500";
	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 2021-01-27 11:00:00 +00:00			`// SPDX-License-Identifier: GPL-2.0+ OR X11`
			`/*`
			`* NXP LS1028A-QDS device tree fragment for RCW 6xxx`
			`*`
net: update NXP copyright text NXP Legal insists that the following are not fine: - Saying "NXP Semiconductors" instead of "NXP", since the company's registered name is "NXP" - Putting a "(c)" sign in the copyright string - Putting a comma in the copyright string The only accepted copyright string format is "Copyright <year-range> NXP". This patch changes the copyright headers in the networking files that were sent by me, or derived from code sent by me. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> 2021-09-17 11:27:13 +00:00			`* Copyright 2019-2021 NXP`
arm: dts: ls1028a: define QDS networking protocol combinations Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 2021-01-27 11:00:00 +00:00			`*/`

			`/*`
			`* This setup is using SCH-30842 cards with AQR112 PHY.`
			`*/`
			`&slot1 {`
			`#include "fsl-sch-30842.dtsi"`
			`};`

			`&enetc0 {`
			`status = "okay";`
			`phy-mode = "sgmii-2500";`
			`phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;`
			`};`