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u-boot/board/ti/dra7xx/evm.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
/*
* (C) Copyright 2013
* Texas Instruments Incorporated, <www.ti.com>
*
* Lokesh Vutla <lokeshvutla@ti.com>
*
* Based on previous work by:
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*/
#include <common.h>
twl6035: rename to palmas TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs Rename twl6035 to palmas to allow reuse across multiple current and future platforms As part of this change, change the CONFIG_TWL6035_POWER to CONFIG_PALMAS_POWER and update usage of header file accordingly. Signed-off-by: Nishanth Menon <nm@ti.com>
2013-03-26 05:20:54 +00:00
#include <palmas.h>
ARM: O5/dra7xx: Add SATA boot support Add the SATA boot support for OMAP5 and dra7xx. Renamed the omap_sata_init to the common init_sata(int dev) for commonality in with sata stack. Added the ROM boot device ID for SATA. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2014-02-03 12:59:02 +00:00
#include <sata.h>
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
#include <linux/string.h>
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
#include <asm/gpio.h>
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
#include <usb.h>
#include <linux/usb/gadget.h>
arm: omap5: add U-Boot FIT signing and SPL image post-processing Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-27 14:19:22 +00:00
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
#include <asm/arch/gpio.h>
ARM: DRA7-evm: Enable IO delay recalibration sequence Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-04 11:12:38 +00:00
#include <asm/arch/dra7xx_iodelay.h>
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
#include <asm/emif.h>
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
ARM: dra7_evm: Add SATA support The evm has a SATA port. Enable SATA configuration and inititialize the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-11-11 14:56:44 +00:00
#include <asm/arch/sata.h>
dra7xx_evm: Add QSPI_4 support, qspiboot build target We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad) read support as well. This means we can be given one of two boot device values, but don't care which it is, so perform a fixup on the QSPI_4 value. We add a qspiboot build target to better show how you would use QSPI as a boot device in deployment. When we boot from QSPI, we can check the environment for 'boot_os' to control Falcon Mode. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2014-04-03 11:52:56 +00:00
#include <environment.h>
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
board: ti: DRA7: Add DP83867 TI phy for rev c Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-30 17:58:37 +00:00
#include <miiphy.h>
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
#include "mux_data.h"
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
#include "../common/board_detect.h"
board: ti: dra76-evm: Add epprom support The dra76-evm is a board based on TI's DRA76 processor Add eeprom support Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:53 +00:00
#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
board: ti: dra71x-evm: Add epprom support The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems such as display audio and is a software compatible derivative of the highly successful DRA74 and DRA72 processor families. More information can be found here[1]. Add epprom detection for dra71-evm. [1] http://www.ti.com/product/dra718 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:24 +00:00
#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
board: ti: dra7xx: complex definitions should be protected with parentheses As a standard practice complex definitions should be protected with parentheses, as it might fail when used in a complex if statements. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-27 07:31:42 +00:00
#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0))
#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
(strncmp("C", board_ti_get_rev(), 1) <= 0))
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
DECLARE_GLOBAL_DATA_PTR;
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
#define SYSINFO_BOARD_NAME_MAX_LEN 37
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
const struct omap_sysinfo sysinfo = {
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
};
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x30717FE3,
.sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
.sdram_config_init = 0x61862BB2,
.sdram_config = 0x61862BB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD1137824,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
board: ti: dra76-evm: Add DDR data dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:55 +00:00
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113783C,
.sdram_tim2 = 0x30B47FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x30B47FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
u64 ram_size;
ram_size = board_ti_get_emif_size();
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
switch (emif_nr) {
case 1:
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*regs = &emif1_ddr3_532_mhz_1cs_2G;
else
*regs = &emif1_ddr3_532_mhz_1cs;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
break;
case 2:
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*regs = &emif2_ddr3_532_mhz_1cs_2G;
else
*regs = &emif2_ddr3_532_mhz_1cs;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
break;
}
break;
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
case DRA762_ABZ_ES1_0:
case DRA762_ACD_ES1_0:
board: ti: dra76-evm: Add DDR data dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:55 +00:00
case DRA762_ES1_0:
if (emif_nr == 1)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
else
*regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
break;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
case DRA722_ES1_0:
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
case DRA722_ES2_0:
ARM: DRA72x: Add support for detection of DRA71x SR 2.1 DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-26 21:51:22 +00:00
case DRA722_ES2_1:
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
}
}
static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x80640300,
.dmm_lisa_map_2 = 0xC0500220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
/*
* DRA722 EVM EMIF1 2GB CONFIGURATION
* EMIF1 4 devices of 512Mb x 8 Micron
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80700100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
u64 ram_size;
ram_size = board_ti_get_emif_size();
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
switch (omap_revision()) {
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
case DRA762_ABZ_ES1_0:
case DRA762_ACD_ES1_0:
board: ti: dra76-evm: Add DDR data dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:55 +00:00
case DRA762_ES1_0:
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
ARM: DRA7: EMIF: Add 4GB DDR settings The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:08 +00:00
if (ram_size > CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_dra7_2GB;
else
*dmm_lisa_regs = &lisa_map_dra7_1536MB;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
break;
case DRA722_ES1_0:
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
case DRA722_ES2_0:
ARM: DRA72x: Add support for detection of DRA71x SR 2.1 DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-26 21:51:22 +00:00
case DRA722_ES2_1:
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
default:
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2;
else
*dmm_lisa_regs = &lisa_map_2G_x_4;
break;
ARM: DRA7: Move emif settings to board specific files The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:06 +00:00
}
}
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
struct vcores_data dra752_volts = {
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
board: ti: dra76-evm: Add the pmic data dra76-evm uses lp8736 and tps65917 pmic for powering on various peripherals. Add data for these pmics and register for dra76-evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:54 +00:00
struct vcores_data dra76x_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = LP87565_REG_ADDR_BUCK01,
.mpu.pmic = &lp87565,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS1,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = LP87565_REG_ADDR_BUCK23,
.gpu.pmic = &lp87565,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS3,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS4,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
struct vcores_data dra722_volts = {
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
/*
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
struct vcores_data dra718_volts = {
/*
* In the case of dra71x GPU MPU and CORE
* are all powered up by BUCK0 of LP873X PMIC
*/
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = LP873X_REG_ADDR_BUCK0,
.mpu.pmic = &lp8733,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = LP873X_REG_ADDR_BUCK0,
.core.pmic = &lp8733,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = LP873X_REG_ADDR_BUCK0,
.gpu.pmic = &lp8733,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
/*
* The DSPEVE and IVA rails are grouped on DRA71x-evm
* and are powered by BUCK1 of LP873X PMIC
*/
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = LP873X_REG_ADDR_BUCK1,
.eve.pmic = &lp8733,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = LP873X_REG_ADDR_BUCK1,
.iva.pmic = &lp8733,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
int get_voltrail_opp(int rail_offset)
{
int opp;
switch (rail_offset) {
case VOLT_MPU:
opp = DRA7_MPU_OPP;
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
/* DRA71x supports only OPP_NOM for MPU */
if (board_is_dra71x_evm())
opp = OPP_NOM;
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
break;
case VOLT_CORE:
opp = DRA7_CORE_OPP;
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
/* DRA71x supports only OPP_NOM for CORE */
if (board_is_dra71x_evm())
opp = OPP_NOM;
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
break;
case VOLT_GPU:
opp = DRA7_GPU_OPP;
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
/* DRA71x supports only OPP_NOM for GPU */
if (board_is_dra71x_evm())
opp = OPP_NOM;
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
break;
case VOLT_EVE:
opp = DRA7_DSPEVE_OPP;
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
/*
* DRA71x does not support OPP_OD for EVE.
* If OPP_OD is selected by menuconfig, fallback
* to OPP_NOM.
*/
if (board_is_dra71x_evm() && opp == OPP_OD)
opp = OPP_NOM;
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
break;
case VOLT_IVA:
opp = DRA7_IVA_OPP;
board: dra71: Fix selection of OPPs As per the DM[1] Dated June 2016–Revised February 2017, Table 5-3, DRA71 supports the following OPPs for various voltage domains: VDD_MPU: OPP_NOM VDD_CORE: OPP_NOM VDD_GPU: OPP_NOM VDD_DSPEVE: OPP_NOM, OPP_HIGH VDD_IVA: OPP_NOM, OPP_HIGH This patch add support for selection of the above OPPs instead of using OPP_NOM for all voltage domains. [1] http://www.ti.com/lit/ds/symlink/dra718.pdf Reported-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-04-20 08:37:52 +00:00
/*
* DRA71x does not support OPP_OD for IVA.
* If OPP_OD is selected by menuconfig, fallback
* to OPP_NOM.
*/
if (board_is_dra71x_evm() && opp == OPP_OD)
opp = OPP_NOM;
ARM: OMAP4+: Add support for dynamically selecting OPPs It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:24:39 +00:00
break;
default:
opp = OPP_NOM;
}
return opp;
}
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
/**
* @brief board_init
*
* @return 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
return 0;
}
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-31 14:40:32 +00:00
int dram_init_banksize(void)
ARM: DRA7-evm: Update memory info in banks Updating the memory banks properly so that DT is populated accordingly. And updating this only after DDR is properly detected by eeprom, so that git bisect is still maintained. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:09 +00:00
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000;
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
}
board_f: Drop setup_dram_config() wrapper By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2017-03-31 14:40:32 +00:00
return 0;
ARM: DRA7-evm: Update memory info in banks Updating the memory banks properly so that DT is populated accordingly. And updating this only after DDR is properly detected by eeprom, so that git bisect is still maintained. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:09 +00:00
}
ARM: dra7_evm: Add SATA support The evm has a SATA port. Enable SATA configuration and inititialize the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-11-11 14:56:44 +00:00
int board_late_init(void)
{
ARM: DRA7xx: Update the board_name env variable Update the board_name env variable and accordingly populate the dtb file. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-07-14 14:27:58 +00:00
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
char *name = "unknown";
ti_omap5_common: Find right dtb file for DRA72-RevC Evm DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-29 09:20:41 +00:00
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
board: ti: dra71x-evm: Add epprom support The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems such as display audio and is a software compatible derivative of the highly successful DRA74 and DRA72 processor families. More information can be found here[1]. Add epprom detection for dra71-evm. [1] http://www.ti.com/product/dra718 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:24 +00:00
else if (board_is_dra71x_evm())
name = "dra71x";
ti_omap5_common: Find right dtb file for DRA72-RevC Evm DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-29 09:20:41 +00:00
else
name = "dra72x";
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
} else if (is_dra76x_abz()) {
name = "dra76x_abz";
} else if (is_dra76x_acd()) {
name = "dra76x_acd";
ti_omap5_common: Find right dtb file for DRA72-RevC Evm DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-29 09:20:41 +00:00
} else {
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
name = "dra7xx";
ti_omap5_common: Find right dtb file for DRA72-RevC Evm DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-06-29 09:20:41 +00:00
}
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
set_board_info_env(name);
ARM: DRA7: Set serial number environment variable This patch populates serial number environment variable from die_id_0 and die_id_1 register values for DRA7xx boards. The function is added in omap common code so that this can be re-used. Serial# environment variable will be useful to show correct information in "fastboot devices" commands. Ref: http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-03-24 22:34:51 +00:00
ARM: DRA7: Make FIT boot as default boot on HS devices Verification has to be done before booting any images on HS devices. So default the boot to FIT on HS devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-29 06:28:01 +00:00
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env: Rename setenv() to env_set() We are now using an env_ prefix for environment functions. Rename setenv() for consistency. Also add function comments in common.h. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:09 +00:00
env_set("boot_fit", "1");
ARM: DRA7: Make FIT boot as default boot on HS devices Verification has to be done before booting any images on HS devices. So default the boot to FIT on HS devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-29 06:28:01 +00:00
omap-common: Common serial and usbethaddr functions based on die id Now that we have a common prototype to grab the omap die id, functions to figure out a serial number and usb ethernet address can use it directly. Those also get an omap_die_id prefix for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-27 17:37:12 +00:00
omap_die_id_serial();
arm: dra7: Set fastboot variables in environment One can obtain those variables using next commands: $ fastboot getvar cpu $ fastboot getvar secure $ fastboot getvar board_rev $ fastboot getvar userdata_size Those variables are needed for fastboot.sh script. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-22 16:16:42 +00:00
omap_set_fastboot_vars();
board: ti: dra71x-evm: Hook LDO1 of LP8733 to EN_PIN All regulators are hooked to EN_Pin at reset so that EN Pin controls their state. Hook the LDO1 regulator to EN pin which at reset is not hooked. This applies only to LP8733. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-10-12 04:48:45 +00:00
/*
* Hook the LDO1 regulator to EN pin. This applies only to LP8733
* Rest all regulators are hooked to EN Pin at reset.
*/
if (board_is_dra71x_evm())
palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
ARM: DRA7xx: Update the board_name env variable Update the board_name env variable and accordingly populate the dtb file. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-07-14 14:27:58 +00:00
#endif
ARM: dra7_evm: Add SATA support The evm has a SATA port. Enable SATA configuration and inititialize the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
2013-11-11 14:56:44 +00:00
return 0;
}
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
#ifdef CONFIG_SPL_BUILD
void do_board_detect(void)
{
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
}
#else
void do_board_detect(void)
{
char *bname = NULL;
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
board: ti: dra71x-evm: Add epprom support The dra71x-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems such as display audio and is a software compatible derivative of the highly successful DRA74 and DRA72 processor families. More information can be found here[1]. Add epprom detection for dra71-evm. [1] http://www.ti.com/product/dra718 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:24 +00:00
} else if (board_is_dra71x_evm()) {
bname = "DRA71x EVM";
board: ti: dra76-evm: Add epprom support The dra76-evm is a board based on TI's DRA76 processor Add eeprom support Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:53 +00:00
} else if (board_is_dra76x_evm()) {
bname = "DRA76x EVM";
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
} else {
board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0 DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:14 +00:00
/* If EEPROM is not populated */
ARM: DRA7: Enable EEPROM support Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-03-08 03:48:05 +00:00
if (is_dra72x())
bname = "DRA72x EVM";
else
bname = "DRA74x EVM";
}
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
#endif /* CONFIG_SPL_BUILD */
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
void vcores_init(void)
{
if (board_is_dra74x_evm()) {
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
board: ti: dra71x-evm: Add PMIC support Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:27 +00:00
} else if (board_is_dra71x_evm()) {
*omap_vcores = &dra718_volts;
board: ti: dra76-evm: Add the pmic data dra76-evm uses lp8736 and tps65917 pmic for powering on various peripherals. Add data for these pmics and register for dra76-evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:54 +00:00
} else if (board_is_dra76x_evm()) {
*omap_vcores = &dra76x_volts;
arm: dra7xx: Assign omap_vcores based on board type Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
2016-06-07 10:35:25 +00:00
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra722_volts;
else
*omap_vcores = &dra752_volts;
}
}
omap-common: Rename set_muxconf_regs_essential to set_muxconf_regs There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
2016-02-27 18:18:56 +00:00
void set_muxconf_regs(void)
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
{
do_set_mux32((*ctrl)->control_padconf_core_base,
ARM: DRA7-evm: Enable IO delay recalibration sequence Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-04 11:12:38 +00:00
early_padconf, ARRAY_SIZE(early_padconf));
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
}
ARM: DRA7-evm: Enable IO delay recalibration sequence Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-04 11:12:38 +00:00
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
struct pad_conf_entry const *pads, *delta_pads = NULL;
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
struct iodelay_cfg_entry const *iodelay;
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
int npads, niodelays, delta_npads = 0;
int ret;
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
switch (omap_revision()) {
case DRA722_ES1_0:
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
case DRA722_ES2_0:
ARM: DRA72x: Add support for detection of DRA71x SR 2.1 DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-26 21:51:22 +00:00
case DRA722_ES2_1:
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
board: ti: dra71x-evm: Add mux settings Add mux and iodelay settings for dra71x-evm. Data generated using PCT_DRA71x_SR2.0_v1.0.0.0 version (June 2016). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:25 +00:00
if (board_is_dra71x_evm()) {
pads = dra71x_core_padconf_array;
npads = ARRAY_SIZE(dra71x_core_padconf_array);
iodelay = dra71_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
} else if (board_is_dra72x_revc_or_later()) {
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
iodelay = dra72_iodelay_cfg_array_revc;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
} else {
delta_pads = dra72x_rgmii_padconf_array_revb;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
iodelay = dra72_iodelay_cfg_array_revb;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
}
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
break;
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
case DRA762_ACD_ES1_0:
board: ti: dra76-evm: Add the pinmux data Adding pinmux and IODELAY data for dra76-evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:56 +00:00
case DRA762_ES1_0:
pads = dra76x_core_padconf_array;
npads = ARRAY_SIZE(dra76x_core_padconf_array);
iodelay = dra76x_es1_0_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
break;
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
default:
case DRA752_ES2_0:
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
case DRA762_ABZ_ES1_0:
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:51:00 +00:00
/* Setup port1 and port2 for rgmii with 'no-id' mode */
clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
RGMII1_ID_MODE_N_MASK);
ARM: DRA74-evm: Add iodelay values for SR2.0 Silicon revision 2.0 has new signal routing hence has an updated set of iodelay parameters to be used. Update the configuration for the same. Padmux remains the same. Based on data from VayuES2_EVM_Base_Config-20150807. NOTE: With respect to the RGMII values, the Manual IODelay values are used for the fine adjusments needed to meet the tight RGMII specification. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-13 14:50:59 +00:00
break;
ARM: DRA7-evm: Add mux data Adding the mux data, manual and virtual mode settings for DRA7-evm. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
2015-06-04 11:12:39 +00:00
}
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
/* Setup I/O isolation */
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
/* Now do the weird minor deltas that should be safe */
if (delta_npads)
do_set_mux32((*ctrl)->control_padconf_core_base,
delta_pads, delta_npads);
board: ti: dra7xx: Select MCAN instead of DCAN on DRA76 EVM MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance to use if any at all is done through CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is handled in U-boot. Handle this additional pinmuxing requirement in U-boot to ensure that MCAN is used by default via the DCAN1 pins. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> [fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN] Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2017-12-12 11:44:27 +00:00
if (is_dra76x())
/* Set mux for MCAN instead of DCAN1 */
clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
MCAN_SEL_ALT_MASK, MCAN_SEL);
board: ti: DRA7: Add DRA72-rev C evm pinmux Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-15 23:09:17 +00:00
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
ARM: DRA7-evm: Enable IO delay recalibration sequence Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2015-06-04 11:12:38 +00:00
}
#endif
mmc: replace CONFIG_GENERIC_MMC with CONFIG_MMC Now CONFIG_GENERIC_MMC and CONFIG_MMC match for all defconfig. We do not need two options for the same feature. Deprecate the former. This commit was generated with the sed script 's/GENERIC_MMC/MMC/' and manual fixup of drivers/mmc/Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-09 11:31:39 +00:00
#if defined(CONFIG_MMC)
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
arm: omap5+: Add board specific ldo powering It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:49 +00:00
void board_mmc_poweron_ldo(uint voltage)
{
if (board_is_dra71x_evm()) {
if (voltage == LDO_VOLT_3V0)
voltage = 0x19;
else if (voltage == LDO_VOLT_1V8)
voltage = 0xa;
lp873x_mmc1_poweron_ldo(voltage);
board: ti: dra76-evm: Add support for powering on mmc ldo ldo4 is used to poweron mmc on dra76-evm. Enable it. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:57 +00:00
} else if (board_is_dra76x_evm()) {
palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
arm: omap5+: Add board specific ldo powering It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:49 +00:00
} else {
palmas: Add support for powering different ldos It is not necessary that ldo1 is used to power on mmc. So, add support for passing ldo registers for powering on mmc. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:50 +00:00
palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
arm: omap5+: Add board specific ldo powering It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:49 +00:00
}
}
ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-30 15:01:52 +00:00
static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104),
.max_freq = 96000000,
};
static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
.hw_rev = "rev11",
.unsupported_caps = MMC_CAP(MMC_HS_200) |
MMC_CAP(UHS_SDR104) |
MMC_CAP(UHS_SDR50),
.max_freq = 48000000,
};
const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
{
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
if (addr == OMAP_HSMMC1_BASE)
return &dra7x_es1_1_mmc1_fixups;
else
return &dra7x_es1_1_mmc23_fixups;
default:
return NULL;
}
}
arm: dra7xx: Add board files for DRA7XX socs Adding new board files for DRA7XX socs. The pad registers layout is changed completely from OMAP5 So introducing the new structure here and also adding the minimal data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishant Kamat <nskamat@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt omap_mmc_init call for last 2 params] Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12 21:29:08 +00:00
#endif
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS1_BASE,
.tx_fifo_resize = false,
.index = 0,
};
static struct dwc3_omap_device usb_otg_ss1_glue = {
.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 0,
};
static struct ti_usb_phy_device usb_phy1_device = {
.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
.index = 0,
};
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS2_BASE,
.tx_fifo_resize = false,
.index = 1,
};
static struct dwc3_omap_device usb_otg_ss2_glue = {
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 1,
};
static struct ti_usb_phy_device usb_phy2_device = {
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
.index = 1,
};
usb: host: xhci-omap: Remove redundant board_usb_init and board_usb_cleanup functions board_usb_init()/_cleanup() should be in board files and don't have a place in the xhci-omap driver. Weak versions for board_usb_init()/_cleanup() already exist in common/usb.c (for host mode) and drivers/usb/gadget/g_dnl.c (for gadget mode). Therefore, remove init and cleanup functions from xhci-omap and implement them in the board files. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-02-15 11:42:11 +00:00
int board_usb_init(int index, enum usb_init_type init)
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
{
board: ti: invoke clock API to enable and disable clocks invoke enable_usb_clocks during board_usb_init and disable_usb_clocks during board_usb_exit to enable and disable clocks respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-19 10:46:27 +00:00
enable_usb_clocks(index);
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy1_device);
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy2_device);
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
return 0;
}
usb: host: xhci-omap: Remove redundant board_usb_init and board_usb_cleanup functions board_usb_init()/_cleanup() should be in board files and don't have a place in the xhci-omap driver. Weak versions for board_usb_init()/_cleanup() already exist in common/usb.c (for host mode) and drivers/usb/gadget/g_dnl.c (for gadget mode). Therefore, remove init and cleanup functions from xhci-omap and implement them in the board files. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-02-15 11:42:11 +00:00
int board_usb_cleanup(int index, enum usb_init_type init)
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
{
switch (index) {
case 0:
case 1:
ti_usb_phy_uboot_exit(index);
dwc3_uboot_exit(index);
dwc3_omap_uboot_exit(index);
break;
default:
printf("Invalid Controller Index\n");
}
board: ti: invoke clock API to enable and disable clocks invoke enable_usb_clocks during board_usb_init and disable_usb_clocks during board_usb_exit to enable and disable clocks respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-19 10:46:27 +00:00
disable_usb_clocks(index);
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
return 0;
}
usb: modify usb_gadget_handle_interrupts to take controller index Since we support multiple dwc3 controllers to be existent at the same time, in order to handle the interrupts of a particular dwc3 controller usb_gadget_handle_interrutps should take controller index as an argument. Hence the API of usb_gadget_handle_interrupts is modified to take controller index as an argument and made the corresponding changes to all the usb_gadget_handle_interrupts calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:23 +00:00
int usb_gadget_handle_interrupts(int index)
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
{
u32 status;
usb: modify usb_gadget_handle_interrupts to take controller index Since we support multiple dwc3 controllers to be existent at the same time, in order to handle the interrupts of a particular dwc3 controller usb_gadget_handle_interrutps should take controller index as an argument. Hence the API of usb_gadget_handle_interrupts is modified to take controller index as an argument and made the corresponding changes to all the usb_gadget_handle_interrupts calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:23 +00:00
status = dwc3_omap_uboot_interrupt_status(index);
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
if (status)
usb: modify usb_gadget_handle_interrupts to take controller index Since we support multiple dwc3 controllers to be existent at the same time, in order to handle the interrupts of a particular dwc3 controller usb_gadget_handle_interrutps should take controller index as an argument. Hence the API of usb_gadget_handle_interrupts is modified to take controller index as an argument and made the corresponding changes to all the usb_gadget_handle_interrupts calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:23 +00:00
dwc3_uboot_handle_interrupt(index);
board: ti: DRA7: added USB initializtion code Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-02-23 13:10:19 +00:00
return 0;
}
#endif
dra7xx_evm: Add QSPI_4 support, qspiboot build target We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad) read support as well. This means we can be given one of two boot device values, but don't care which it is, so perform a fixup on the QSPI_4 value. We add a qspiboot build target to better show how you would use QSPI as a boot device in deployment. When we boot from QSPI, we can check the environment for 'boot_os' to control Falcon Mode. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2014-04-03 11:52:56 +00:00
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env: Drop env_relocate_spec() in favour of env_load() This is a strange name for a function that loads the environment. There is now only one implementation of this function, so use the new env_load() function directly instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-03 18:22:07 +00:00
env_load();
env: Rename getenv_hex(), getenv_yesno(), getenv_ulong() We are now using an env_ prefix for environment functions. Rename these for consistency. Also add function comments in common.h. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:13 +00:00
if (env_get_yesno("boot_os") != 1)
dra7xx_evm: Add QSPI_4 support, qspiboot build target We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad) read support as well. This means we can be given one of two boot device values, but don't care which it is, so perform a fixup on the QSPI_4 value. We add a qspiboot build target to better show how you would use QSPI as a boot device in deployment. When we boot from QSPI, we can check the environment for 'boot_os' to control Falcon Mode. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2014-04-03 11:52:56 +00:00
return 1;
#endif
return 0;
}
#endif
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
#ifdef CONFIG_DRIVER_TI_CPSW
ARM: dra7_evm: Add Ethernet support for dra72x platform Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-05-22 09:07:12 +00:00
extern u32 *const omap_si_rev;
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
drivers: net: cpsw: add support to have phy address from cpsw platform data Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
2014-02-18 12:31:52 +00:00
.phy_addr = 2,
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
drivers: net: cpsw: add support to have phy address from cpsw platform data Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
2014-02-18 12:31:52 +00:00
.phy_addr = 3,
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
ARM: dra7_evm: Add Ethernet support for dra72x platform Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-05-22 09:07:12 +00:00
.slaves = 2,
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
ARM: dra7_evm: read mac address properly from e-fuse Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-01-07 14:27:38 +00:00
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
ARM: dra7_evm: read mac address properly from e-fuse Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-01-07 14:27:38 +00:00
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
ARM: dra7_evm: read mac address properly from e-fuse Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is not working on some boards, modifying the offset to read properly. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-01-07 14:27:38 +00:00
mac_addr[5] = mac_lo & 0xFF;
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
env: Rename getenv/_f() to env_get() We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:12 +00:00
if (!env_get("ethaddr")) {
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
net: cosmetic: Name ethaddr variables consistently Use "_ethaddr" at the end of variables and drop CamelCase. Make constant values actually 'const'. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-08 06:41:04 +00:00
if (is_valid_ethaddr(mac_addr))
env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr() Rename this function for consistency with env_set(). Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:11 +00:00
eth_env_set_enetaddr("ethaddr", mac_addr);
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
}
ARM: DRA7xx: add support for reading cpsw 2nd mac from efuse Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also correct the bit masking of mac id read from the efuse. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-02-18 12:31:56 +00:00
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
env: Rename getenv/_f() to env_get() We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:12 +00:00
if (!env_get("eth1addr")) {
net: cosmetic: Name ethaddr variables consistently Use "_ethaddr" at the end of variables and drop CamelCase. Make constant values actually 'const'. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-08 06:41:04 +00:00
if (is_valid_ethaddr(mac_addr))
env: Rename eth_setenv_enetaddr() to eth_env_set_enetaddr() Rename this function for consistency with env_set(). Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-03 18:22:11 +00:00
eth_env_set_enetaddr("eth1addr", mac_addr);
ARM: DRA7xx: add support for reading cpsw 2nd mac from efuse Adding support for reading cpsw 2nd mac address from efuse and pass it to kernel via dtb which will be used in dual emac mode of cpsw. Also correct the bit masking of mac id read from the efuse. Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-02-18 12:31:56 +00:00
}
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
ARM: dra7_evm: Add Ethernet support for dra72x platform Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-05-22 09:07:12 +00:00
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
board: ti: DRA7: Add DP83867 TI phy for rev c Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-30 17:58:37 +00:00
if (board_is_dra72x_revc_or_later()) {
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
}
ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-08 10:34:41 +00:00
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
return ret;
}
#endif
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
board: ti: dra76-evm: Add DDR data dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-08-21 07:20:55 +00:00
/* Do not enable VTT for DRA722 or DRA76x */
if (is_dra72x() || is_dra76x())
ARM: DRA: Enable VTT regulator DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-04 14:12:24 +00:00
return;
/*
* EVM Rev G and later use gpio7_11 for DDR3 termination.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
int board_early_init_f(void)
{
vtt_regulator_enable();
return 0;
}
#endif
ARM: omap5: add ft_board_setup for dra7xx/am57xx Adds the board specific ft_board_setup() functions that are called when CONFIG_OF_BOARD_SETUP is defined. These functions will currently just call the ft_cpu_setup() function. Adds CONFIG_OF_BOARD_SETUP to the defconfig files for dra72_evm, dra74_evm, and am57xx_evm. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Madan Srinivas <madans@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-05-20 00:10:54 +00:00
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
return 0;
}
#endif
board: dra7: fit: add support for selecting dtb dynamically FIT allows for a multiple dtb in a single image. SPL needs a way to detect the right dtb to be used. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-05-16 05:21:23 +00:00
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
ARM: dts: dra72: add rev C evm support Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-27 07:31:41 +00:00
if (is_dra72x()) {
ARM: dts: dra71x-evm: Add DT support Add DT support for dra71-evm and built it as part of FIT image. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-23 07:55:30 +00:00
if (board_is_dra71x_evm()) {
if (!strcmp(name, "dra71-evm"))
return 0;
}else if(board_is_dra72x_revc_or_later()) {
ARM: dts: dra72: add rev C evm support Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-27 07:31:41 +00:00
if (!strcmp(name, "dra72-evm-revc"))
return 0;
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
} else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
board: ti: dra76: Add dt support Add support for selecting proper dtb for dra76x u-boot from FIT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-08-21 07:21:01 +00:00
return 0;
arm: dra762: Add support for device package identification DRA762 comes in two packages: - ABZ: Pin compatible package with DRA742 with DDR@1333MHz - ACD: High performance(OPP_PLUS) package with new IPs Both the above packages uses the same IDCODE hence needs to differentiate using package information in DIE_ID_2. Add support for the same. Also update clock, ddr, emif information. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-12-29 06:17:51 +00:00
} else if (!is_dra72x() && !is_dra76x_acd() &&
!strcmp(name, "dra7-evm")) {
board: dra7: fit: add support for selecting dtb dynamically FIT allows for a multiple dtb in a single image. SPL needs a way to detect the right dtb to be used. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-05-16 05:21:23 +00:00
return 0;
ARM: dts: dra72: add rev C evm support Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-27 07:31:41 +00:00
}
return -1;
board: dra7: fit: add support for selecting dtb dynamically FIT allows for a multiple dtb in a single image. SPL needs a way to detect the right dtb to be used. Adding support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-05-16 05:21:23 +00:00
}
#endif
arm: omap5: add U-Boot FIT signing and SPL image post-processing Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-27 14:19:22 +00:00
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
board: ti: dra7xx: add FIT image TEE processing Populate the corresponding TEE image processing call to be performed during FIT loadable processing. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-29 22:33:25 +00:00
void board_tee_image_process(ulong tee_image, size_t tee_size)
{
secure_tee_install((u32)tee_image);
}
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
arm: omap5: add U-Boot FIT signing and SPL image post-processing Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-27 14:19:22 +00:00
#endif
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