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u-boot/arch/arm/mach-rockchip/rk3399/rk3399.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
/*
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
rockchip: use 'arch-rockchip' as header file path Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-28 03:01:23 +00:00
#include <spl_gpio.h>
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
#include <asm/armv8/mmu.h>
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
#include <asm/io.h>
rockchip: rk3399: include gpio.h After applying the series for debug_uart_init(), Travis-CI reports: arch/arm/mach-rockchip/rk3399/rk3399.c:90:2: error: implicit declaration of function 'spl_gpio_set_pull' [-Werror=implicit-function-declaration] spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); ^~~~~~~~~~~~~~~~~ This is caused by a missing header-file include. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-04-29 17:05:26 +00:00
#include <asm/arch-rockchip/gpio.h>
rockchip: rk3399: use grf structure to access reg Prefer to use structure to access register if we could. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:06 +00:00
#include <asm/arch-rockchip/grf_rk3399.h>
rockchip: use 'arch-rockchip' as header file path Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-28 03:01:23 +00:00
#include <asm/arch-rockchip/hardware.h>
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
rockchip: correct the bank0 ram size The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-23 08:11:11 +00:00
DECLARE_GLOBAL_DATA_PTR;
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
#define GRF_EMMCCORE_CON11 0xff77f02c
rockchip: rk3399: use grf structure to access reg Prefer to use structure to access register if we could. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:06 +00:00
#define GRF_BASE 0xff770000
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
static struct mm_region rk3399_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
rockchip: rk3399: correct memory region RK3399 device memory region is 0xf8000000~0xffffffff. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 08:42:44 +00:00
.size = 0xf8000000UL,
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
rockchip: rk3399: correct memory region RK3399 device memory region is 0xf8000000~0xffffffff. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 08:42:44 +00:00
.virt = 0xf8000000UL,
.phys = 0xf8000000UL,
.size = 0x08000000UL,
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = rk3399_mem_map;
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
rockchip: correct the bank0 ram size The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-23 08:11:11 +00:00
int dram_init_banksize(void)
{
size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
/* Reserve 0x200000 for ATF bl31 */
gd->bd->bi_dram[0].start = 0x200000;
gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
return 0;
}
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
rockchip: rk3399: use grf structure to access reg Prefer to use structure to access register if we could. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:06 +00:00
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
/* Emmc clock generator: disable the clock multipilier */
rockchip: rk3399: use grf structure to access reg Prefer to use structure to access register if we could. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:06 +00:00
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
rk3399: disable the clock multiplier support when SoC init The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-07 07:56:16 +00:00
return 0;
}
rockchip: rk3399: add board_debug_uart_init() Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file for all rockchip SoCs later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:07 +00:00
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#define GRF_BASE 0xff770000
#define GPIO0_BASE 0xff720000
#define PMUGRF_BASE 0xff320000
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
#endif
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
/* Enable early UART0 on the RK3399 */
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C0_SEL_MASK,
GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C1_SEL_MASK,
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
rockchip: rk3399: Add option to print on UART3. The RK3399 SPL does not use a pinctrl driver to setup the UART pins. Instead it works based on config macros, which set the base address of the actual UART block. Currently the RK3399 SPL support UART0 and UART2. This patch adds UART3 in the same way as UART0. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-07 08:58:43 +00:00
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
/* Enable early UART3 on the RK3399 */
rk_clrsetreg(&grf->gpio3b_iomux,
GRF_GPIO3B6_SEL_MASK,
GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
rk_clrsetreg(&grf->gpio3b_iomux,
GRF_GPIO3B7_SEL_MASK,
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
rockchip: rk3399: add board_debug_uart_init() Use board_debug_uart_init() for UART iomux init instead of do it in board_init_f, and move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file for all rockchip SoCs later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-29 01:09:07 +00:00
#else
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
rk_setreg(&grf->io_vsel, 1 << 0);
/*
* Let's enable these power rails here, we are already running the SPI
* Flash based code.
*/
spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
/* Set channel C as UART2 input */
rk_clrsetreg(&grf->soc_con7,
GRF_UART_DBG_SEL_MASK,
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
#endif
}
#endif
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