u-boot/board/google/chromebook_link/Kconfig

if TARGET_CHROMEBOOK_LINK

config SYS_BOARD
	default "chromebook_link"

config SYS_VENDOR
	default "google"

config SYS_SOC
	default "ivybridge"

config SYS_CONFIG_NAME
	default "chromebook_link"

config BOARD_SPECIFIC_OPTIONS # dummy
	def_bool y
	select CPU_INTEL_SOCKET_RPGA989
	select NORTHBRIDGE_INTEL_IVYBRIDGE
	select SOUTHBRIDGE_INTEL_C216
	select HAVE_ACPI_RESUME
	select MARK_GRAPHICS_MEM_WRCOMB

config MMCONF_BASE_ADDRESS
	hex
	default 0xf0000000

config EARLY_POST_CROS_EC
	bool "Enable early post to Chrome OS EC"
	default y

endif
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:07 +00:00			`if TARGET_CHROMEBOOK_LINK`

			`config SYS_BOARD`
			`default "chromebook_link"`

			`config SYS_VENDOR`
			`default "google"`

			`config SYS_SOC`
			`default "ivybridge"`

			`config SYS_CONFIG_NAME`
			`default "chromebook_link"`

x86: chromebook_link: Implement CAR support (cache as RAM) Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:10 +00:00			`config BOARD_SPECIFIC_OPTIONS # dummy`
			`def_bool y`
			`select CPU_INTEL_SOCKET_RPGA989`
			`select NORTHBRIDGE_INTEL_IVYBRIDGE`
			`select SOUTHBRIDGE_INTEL_C216`
			`select HAVE_ACPI_RESUME`
			`select MARK_GRAPHICS_MEM_WRCOMB`

			`config MMCONF_BASE_ADDRESS`
			`hex`
			`default 0xf0000000`

x86: Emit post codes in startup code for Chromebooks On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 2014-11-13 05:42:09 +00:00			`config EARLY_POST_CROS_EC`
			`bool "Enable early post to Chrome OS EC"`
			`default y`

x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 05:42:07 +00:00			`endif`