2003-06-20 22:36:30 +00:00
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/*
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* (C) Copyright 2001
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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2003-07-14 22:13:32 +00:00
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* Modified during 2003 by
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* Ken Chou, kchou@ieee.org
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2003-06-20 22:36:30 +00:00
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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2008-08-31 17:07:16 +00:00
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#include <netdev.h>
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2003-06-20 22:36:30 +00:00
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int checkboard (void)
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{
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ulong busfreq = get_bus_freq(0);
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char buf[32];
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printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
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return 0;
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}
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2008-06-09 21:03:40 +00:00
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phys_size_t initdram (int board_type)
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2003-06-20 22:36:30 +00:00
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{
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2004-01-06 22:38:14 +00:00
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long size;
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long new_bank0_end;
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long mear1;
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long emear1;
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2003-06-20 22:36:30 +00:00
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2008-10-16 13:01:15 +00:00
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size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
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2003-06-20 22:36:30 +00:00
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2004-01-06 22:38:14 +00:00
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new_bank0_end = size - 1;
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mear1 = mpc824x_mpc107_getreg(MEAR1);
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emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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2003-06-20 22:36:30 +00:00
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2004-01-06 22:38:14 +00:00
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return (size);
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2003-06-20 22:36:30 +00:00
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}
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/*
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* Initialize PCI Devices
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_a3000_config_table[] = {
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2003-07-16 21:53:01 +00:00
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/* vendor, device, class */
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/* bus, dev, func */
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2003-07-14 22:13:32 +00:00
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{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
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2003-07-16 21:53:01 +00:00
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
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2003-06-20 22:36:30 +00:00
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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2003-07-16 21:53:01 +00:00
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PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
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2003-06-20 22:36:30 +00:00
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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2008-05-20 14:00:29 +00:00
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PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
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2003-06-20 22:36:30 +00:00
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pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
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PCI_ENET2_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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2003-07-14 22:13:32 +00:00
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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2003-07-16 21:53:01 +00:00
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PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
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2003-07-14 22:13:32 +00:00
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pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
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PCI_ENET3_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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2003-06-20 22:36:30 +00:00
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_a3000_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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2008-08-31 17:07:16 +00:00
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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