2018-04-16 03:35:33 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier PXs3 SoC
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//
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// Copyright (C) 2017 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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2017-01-21 09:05:30 +00:00
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2017-11-24 15:25:35 +00:00
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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2020-07-09 06:08:14 +00:00
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#include <dt-bindings/thermal/thermal.h>
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2017-11-24 15:25:35 +00:00
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2017-01-21 09:05:30 +00:00
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/ {
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compatible = "socionext,uniphier-pxs3";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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2019-04-12 09:55:50 +00:00
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compatible = "arm,cortex-a53";
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2017-01-21 09:05:30 +00:00
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reg = <0 0x000>;
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2017-08-29 03:20:53 +00:00
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clocks = <&sys_clk 33>;
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2017-01-21 09:05:30 +00:00
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enable-method = "psci";
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2017-08-29 03:20:53 +00:00
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operating-points-v2 = <&cluster0_opp>;
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2020-07-09 06:08:14 +00:00
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#cooling-cells = <2>;
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2017-01-21 09:05:30 +00:00
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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2019-04-12 09:55:50 +00:00
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compatible = "arm,cortex-a53";
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2017-01-21 09:05:30 +00:00
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reg = <0 0x001>;
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2017-08-29 03:20:53 +00:00
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clocks = <&sys_clk 33>;
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2017-01-21 09:05:30 +00:00
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enable-method = "psci";
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2017-08-29 03:20:53 +00:00
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operating-points-v2 = <&cluster0_opp>;
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2020-07-09 06:08:14 +00:00
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#cooling-cells = <2>;
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2017-01-21 09:05:30 +00:00
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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2019-04-12 09:55:50 +00:00
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compatible = "arm,cortex-a53";
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2017-01-21 09:05:30 +00:00
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reg = <0 0x002>;
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2017-08-29 03:20:53 +00:00
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clocks = <&sys_clk 33>;
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2017-01-21 09:05:30 +00:00
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enable-method = "psci";
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2017-08-29 03:20:53 +00:00
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operating-points-v2 = <&cluster0_opp>;
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2020-07-09 06:08:14 +00:00
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#cooling-cells = <2>;
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2017-01-21 09:05:30 +00:00
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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2019-04-12 09:55:50 +00:00
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compatible = "arm,cortex-a53";
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2017-01-21 09:05:30 +00:00
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reg = <0 0x003>;
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2017-08-29 03:20:53 +00:00
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clocks = <&sys_clk 33>;
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2017-01-21 09:05:30 +00:00
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enable-method = "psci";
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2017-08-29 03:20:53 +00:00
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operating-points-v2 = <&cluster0_opp>;
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2020-07-09 06:08:14 +00:00
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#cooling-cells = <2>;
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2017-08-29 03:20:53 +00:00
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};
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};
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2017-11-24 15:25:35 +00:00
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cluster0_opp: opp-table {
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2017-08-29 03:20:53 +00:00
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-866667000 {
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opp-hz = /bits/ 64 <866667000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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clock-latency-ns = <300>;
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2017-01-21 09:05:30 +00:00
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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2017-11-24 15:25:35 +00:00
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
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};
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2017-01-21 09:05:30 +00:00
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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2020-07-09 06:08:14 +00:00
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>; /* 250ms */
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polling-delay = <1000>; /* 1000ms */
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thermal-sensors = <&pvtctl>;
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trips {
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cpu_crit: cpu-crit {
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temperature = <110000>; /* 110C */
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_alert: cpu-alert {
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temperature = <100000>; /* 100C */
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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2019-07-10 11:07:29 +00:00
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-memory@81000000 {
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reg = <0x0 0x81000000 0x0 0x01000000>;
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no-map;
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};
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};
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2017-03-12 15:16:40 +00:00
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soc@0 {
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2017-01-21 09:05:30 +00:00
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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2018-12-19 11:03:21 +00:00
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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2020-07-09 06:08:14 +00:00
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#address-cells = <1>;
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#size-cells = <0>;
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2018-12-19 11:03:21 +00:00
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi1: spi@54006100 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006100 0x100>;
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2020-07-09 06:08:14 +00:00
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#address-cells = <1>;
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#size-cells = <0>;
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2018-12-19 11:03:21 +00:00
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interrupts = <0 216 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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2020-07-09 06:08:14 +00:00
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clocks = <&peri_clk 12>;
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resets = <&peri_rst 12>;
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2018-12-19 11:03:21 +00:00
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};
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2017-01-21 09:05:30 +00:00
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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2017-11-24 15:25:35 +00:00
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resets = <&peri_rst 0>;
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2017-01-21 09:05:30 +00:00
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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2017-11-24 15:25:35 +00:00
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resets = <&peri_rst 1>;
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2017-01-21 09:05:30 +00:00
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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2017-11-24 15:25:35 +00:00
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resets = <&peri_rst 2>;
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2017-01-21 09:05:30 +00:00
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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2017-11-24 15:25:35 +00:00
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resets = <&peri_rst 3>;
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2017-01-21 09:05:30 +00:00
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};
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2017-08-29 03:20:53 +00:00
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gpio: gpio@55000000 {
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2017-10-13 10:21:52 +00:00
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compatible = "socionext,uniphier-gpio";
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2017-08-29 03:20:53 +00:00
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>,
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2018-03-15 02:43:03 +00:00
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<&pinctrl 104 0 0>,
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<&pinctrl 168 0 0>;
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2017-08-29 03:20:53 +00:00
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gpio-ranges-group-names = "gpio_range0",
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"gpio_range1",
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"gpio_range2";
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2017-10-13 10:21:52 +00:00
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ngpios = <286>;
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2017-11-24 15:25:35 +00:00
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
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<21 217 3>;
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2017-08-29 03:20:53 +00:00
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};
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2017-01-21 09:05:30 +00:00
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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2017-11-24 15:25:35 +00:00
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resets = <&peri_rst 4>;
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2017-01-21 09:05:30 +00:00
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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|
interrupts = <0 42 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
|
|
|
clocks = <&peri_clk 5>;
|
2017-11-24 15:25:35 +00:00
|
|
|
resets = <&peri_rst 5>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@58782000 {
|
|
|
|
|
compatible = "socionext,uniphier-fi2c";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x58782000 0x80>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
interrupts = <0 43 4>;
|
2017-08-29 03:20:53 +00:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clocks = <&peri_clk 6>;
|
2017-11-24 15:25:35 +00:00
|
|
|
resets = <&peri_rst 6>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@58783000 {
|
|
|
|
|
compatible = "socionext,uniphier-fi2c";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x58783000 0x80>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
interrupts = <0 44 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
|
|
|
clocks = <&peri_clk 7>;
|
2017-11-24 15:25:35 +00:00
|
|
|
resets = <&peri_rst 7>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* chip-internal connection for HDMI */
|
|
|
|
|
i2c6: i2c@58786000 {
|
|
|
|
|
compatible = "socionext,uniphier-fi2c";
|
|
|
|
|
reg = <0x58786000 0x80>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
interrupts = <0 26 4>;
|
|
|
|
|
clocks = <&peri_clk 10>;
|
2017-11-24 15:25:35 +00:00
|
|
|
resets = <&peri_rst 10>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
system_bus: system-bus@58c00000 {
|
|
|
|
|
compatible = "socionext,uniphier-system-bus";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x58c00000 0x400>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_system_bus>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-05-15 05:23:46 +00:00
|
|
|
smpctrl@59801000 {
|
2017-01-21 09:05:30 +00:00
|
|
|
compatible = "socionext,uniphier-smpctrl";
|
|
|
|
|
reg = <0x59801000 0x400>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdctrl@59810000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-sdctrl",
|
|
|
|
|
"simple-mfd", "syscon";
|
2017-08-29 03:20:53 +00:00
|
|
|
reg = <0x59810000 0x400>;
|
2017-01-21 09:05:30 +00:00
|
|
|
|
|
|
|
|
sd_clk: clock {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-sd-clock";
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd_rst: reset {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-sd-reset";
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
perictrl@59820000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-perictrl",
|
|
|
|
|
"simple-mfd", "syscon";
|
|
|
|
|
reg = <0x59820000 0x200>;
|
|
|
|
|
|
|
|
|
|
peri_clk: clock {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-peri-clock";
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
peri_rst: reset {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-peri-reset";
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-02-28 12:57:19 +00:00
|
|
|
emmc: mmc@5a000000 {
|
2017-01-21 09:05:30 +00:00
|
|
|
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
|
|
|
|
reg = <0x5a000000 0x400>;
|
|
|
|
|
interrupts = <0 78 4>;
|
|
|
|
|
pinctrl-names = "default";
|
2018-09-10 03:58:32 +00:00
|
|
|
pinctrl-0 = <&pinctrl_emmc>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clocks = <&sys_clk 4>;
|
2017-11-24 15:25:35 +00:00
|
|
|
resets = <&sys_rst 4>;
|
2017-01-21 09:05:30 +00:00
|
|
|
bus-width = <8>;
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
mmc-hs200-1_8v;
|
2017-11-24 15:25:35 +00:00
|
|
|
mmc-pwrseq = <&emmc_pwrseq>;
|
2018-05-22 15:30:54 +00:00
|
|
|
cdns,phy-input-delay-legacy = <9>;
|
2017-08-29 03:20:53 +00:00
|
|
|
cdns,phy-input-delay-mmc-highspeed = <2>;
|
|
|
|
|
cdns,phy-input-delay-mmc-ddr = <3>;
|
|
|
|
|
cdns,phy-dll-delay-sdclk = <21>;
|
|
|
|
|
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
2017-01-21 09:05:30 +00:00
|
|
|
};
|
|
|
|
|
|
2020-02-28 12:57:19 +00:00
|
|
|
sd: mmc@5a400000 {
|
2018-09-10 03:58:35 +00:00
|
|
|
compatible = "socionext,uniphier-sd-v3.1.1";
|
2017-01-21 09:05:30 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x5a400000 0x800>;
|
|
|
|
|
interrupts = <0 76 4>;
|
2018-09-10 03:58:35 +00:00
|
|
|
pinctrl-names = "default", "uhs";
|
2017-01-21 09:05:30 +00:00
|
|
|
pinctrl-0 = <&pinctrl_sd>;
|
2018-09-10 03:58:35 +00:00
|
|
|
pinctrl-1 = <&pinctrl_sd_uhs>;
|
2017-01-21 09:05:30 +00:00
|
|
|
clocks = <&sd_clk 0>;
|
|
|
|
|
reset-names = "host";
|
|
|
|
|
resets = <&sd_rst 0>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
cap-sd-highspeed;
|
2018-09-10 03:58:35 +00:00
|
|
|
sd-uhs-sdr12;
|
|
|
|
|
sd-uhs-sdr25;
|
|
|
|
|
sd-uhs-sdr50;
|
2017-01-21 09:05:30 +00:00
|
|
|
};
|
|
|
|
|
|
2018-04-16 03:35:33 +00:00
|
|
|
soc_glue: soc-glue@5f800000 {
|
2017-01-21 09:05:30 +00:00
|
|
|
compatible = "socionext,uniphier-pxs3-soc-glue",
|
|
|
|
|
"simple-mfd", "syscon";
|
|
|
|
|
reg = <0x5f800000 0x2000>;
|
|
|
|
|
|
|
|
|
|
pinctrl: pinctrl {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-pinctrl";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2017-11-24 15:25:35 +00:00
|
|
|
soc-glue@5f900000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-soc-glue-debug",
|
|
|
|
|
"simple-mfd";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x5f900000 0x2000>;
|
|
|
|
|
|
|
|
|
|
efuse@100 {
|
|
|
|
|
compatible = "socionext,uniphier-efuse";
|
|
|
|
|
reg = <0x100 0x28>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
efuse@200 {
|
|
|
|
|
compatible = "socionext,uniphier-efuse";
|
|
|
|
|
reg = <0x200 0x68>;
|
2018-12-19 11:03:21 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
|
|
|
|
/* USB cells */
|
|
|
|
|
usb_rterm0: trim@54,4 {
|
|
|
|
|
reg = <0x54 1>;
|
|
|
|
|
bits = <4 2>;
|
|
|
|
|
};
|
|
|
|
|
usb_rterm1: trim@55,4 {
|
|
|
|
|
reg = <0x55 1>;
|
|
|
|
|
bits = <4 2>;
|
|
|
|
|
};
|
|
|
|
|
usb_rterm2: trim@58,4 {
|
|
|
|
|
reg = <0x58 1>;
|
|
|
|
|
bits = <4 2>;
|
|
|
|
|
};
|
|
|
|
|
usb_rterm3: trim@59,4 {
|
|
|
|
|
reg = <0x59 1>;
|
|
|
|
|
bits = <4 2>;
|
|
|
|
|
};
|
|
|
|
|
usb_sel_t0: trim@54,0 {
|
|
|
|
|
reg = <0x54 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
|
|
|
|
usb_sel_t1: trim@55,0 {
|
|
|
|
|
reg = <0x55 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
|
|
|
|
usb_sel_t2: trim@58,0 {
|
|
|
|
|
reg = <0x58 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
|
|
|
|
usb_sel_t3: trim@59,0 {
|
|
|
|
|
reg = <0x59 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
|
|
|
|
usb_hs_i0: trim@56,0 {
|
|
|
|
|
reg = <0x56 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
|
|
|
|
usb_hs_i2: trim@5a,0 {
|
|
|
|
|
reg = <0x5a 1>;
|
|
|
|
|
bits = <0 4>;
|
|
|
|
|
};
|
2017-11-24 15:25:35 +00:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-09 06:08:14 +00:00
|
|
|
xdmac: dma-controller@5fc10000 {
|
|
|
|
|
compatible = "socionext,uniphier-xdmac";
|
|
|
|
|
reg = <0x5fc10000 0x5300>;
|
|
|
|
|
interrupts = <0 188 4>;
|
|
|
|
|
dma-channels = <16>;
|
|
|
|
|
#dma-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-02-28 12:57:19 +00:00
|
|
|
aidet: interrupt-controller@5fc20000 {
|
2017-08-29 03:20:53 +00:00
|
|
|
compatible = "socionext,uniphier-pxs3-aidet";
|
2017-01-21 09:05:30 +00:00
|
|
|
reg = <0x5fc20000 0x200>;
|
2017-08-29 03:20:53 +00:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2017-01-21 09:05:30 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gic: interrupt-controller@5fe00000 {
|
|
|
|
|
compatible = "arm,gic-v3";
|
|
|
|
|
reg = <0x5fe00000 0x10000>, /* GICD */
|
|
|
|
|
<0x5fe80000 0x80000>; /* GICR */
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
interrupts = <1 9 4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sysctrl@61840000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-sysctrl",
|
|
|
|
|
"simple-mfd", "syscon";
|
|
|
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
|
|
|
|
|
|
sys_clk: clock {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-clock";
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sys_rst: reset {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-reset";
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
2017-08-29 03:20:53 +00:00
|
|
|
|
|
|
|
|
watchdog {
|
|
|
|
|
compatible = "socionext,uniphier-wdt";
|
|
|
|
|
};
|
2020-07-09 06:08:14 +00:00
|
|
|
|
|
|
|
|
pvtctl: pvtctl {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-thermal";
|
|
|
|
|
interrupts = <0 3 4>;
|
|
|
|
|
#thermal-sensor-cells = <0>;
|
|
|
|
|
socionext,tmod-calibration = <0x0f22 0x68ee>;
|
|
|
|
|
};
|
2017-08-29 03:20:53 +00:00
|
|
|
};
|
|
|
|
|
|
2018-04-16 03:35:33 +00:00
|
|
|
eth0: ethernet@65000000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-ave4";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65000000 0x8500>;
|
|
|
|
|
interrupts = <0 66 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_ether_rgmii>;
|
2018-05-11 09:49:16 +00:00
|
|
|
clock-names = "ether";
|
2018-04-16 03:35:33 +00:00
|
|
|
clocks = <&sys_clk 6>;
|
2018-05-11 09:49:16 +00:00
|
|
|
reset-names = "ether";
|
2018-04-16 03:35:33 +00:00
|
|
|
resets = <&sys_rst 6>;
|
2022-07-13 01:59:45 +00:00
|
|
|
phy-mode = "rgmii-id";
|
2018-04-16 03:35:33 +00:00
|
|
|
local-mac-address = [00 00 00 00 00 00];
|
2018-05-11 09:49:14 +00:00
|
|
|
socionext,syscon-phy-mode = <&soc_glue 0>;
|
2018-04-16 03:35:33 +00:00
|
|
|
|
|
|
|
|
mdio0: mdio {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
eth1: ethernet@65200000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-ave4";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65200000 0x8500>;
|
|
|
|
|
interrupts = <0 67 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_ether1_rgmii>;
|
2018-05-11 09:49:16 +00:00
|
|
|
clock-names = "ether";
|
2018-04-16 03:35:33 +00:00
|
|
|
clocks = <&sys_clk 7>;
|
2018-05-11 09:49:16 +00:00
|
|
|
reset-names = "ether";
|
2018-04-16 03:35:33 +00:00
|
|
|
resets = <&sys_rst 7>;
|
2022-07-13 01:59:45 +00:00
|
|
|
phy-mode = "rgmii-id";
|
2018-04-16 03:35:33 +00:00
|
|
|
local-mac-address = [00 00 00 00 00 00];
|
2018-05-11 09:49:14 +00:00
|
|
|
socionext,syscon-phy-mode = <&soc_glue 1>;
|
2018-04-16 03:35:33 +00:00
|
|
|
|
|
|
|
|
mdio1: mdio {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2018-12-19 11:03:21 +00:00
|
|
|
_usb0: usb@65a00000 {
|
|
|
|
|
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65a00000 0xcd00>;
|
|
|
|
|
interrupt-names = "host", "peripheral";
|
|
|
|
|
interrupts = <0 134 4>, <0 135 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
|
|
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
|
|
|
clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
|
|
|
|
|
resets = <&usb0_rst 15>;
|
|
|
|
|
phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
|
|
|
|
|
<&usb0_ssphy0>, <&usb0_ssphy1>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-glue@65b00000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
|
|
|
|
"simple-mfd";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x65b00000 0x400>;
|
|
|
|
|
|
|
|
|
|
usb0_rst: reset@0 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
|
|
|
|
reg = <0x0 0x4>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 12>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 12>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_vbus0: regulator@100 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
|
|
|
|
reg = <0x100 0x10>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 12>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 12>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_vbus1: regulator@110 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
|
|
|
|
reg = <0x110 0x10>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 12>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 12>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_hsphy0: hs-phy@200 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
|
|
|
|
reg = <0x200 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy";
|
|
|
|
|
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 12>, <&sys_rst 16>;
|
|
|
|
|
vbus-supply = <&usb0_vbus0>;
|
|
|
|
|
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
|
|
|
|
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
|
|
|
|
|
<&usb_hs_i0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_hsphy1: hs-phy@210 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
|
|
|
|
reg = <0x210 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy";
|
|
|
|
|
clocks = <&sys_clk 12>, <&sys_clk 16>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 12>, <&sys_rst 16>;
|
|
|
|
|
vbus-supply = <&usb0_vbus1>;
|
|
|
|
|
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
|
|
|
|
nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
|
|
|
|
|
<&usb_hs_i0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_ssphy0: ss-phy@300 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
|
|
|
|
reg = <0x300 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy";
|
|
|
|
|
clocks = <&sys_clk 12>, <&sys_clk 17>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 12>, <&sys_rst 17>;
|
|
|
|
|
vbus-supply = <&usb0_vbus0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_ssphy1: ss-phy@310 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
|
|
|
|
reg = <0x310 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy";
|
|
|
|
|
clocks = <&sys_clk 12>, <&sys_clk 18>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 12>, <&sys_rst 18>;
|
|
|
|
|
vbus-supply = <&usb0_vbus1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* FIXME: U-Boot own node */
|
2017-08-29 03:20:53 +00:00
|
|
|
usb0: usb@65b00000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-dwc3";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65b00000 0x1000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
|
|
|
|
dwc3@65a00000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x65a00000 0x10000>;
|
|
|
|
|
interrupts = <0 134 4>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
tx-fifo-resize;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2018-12-19 11:03:21 +00:00
|
|
|
_usb1: usb@65c00000 {
|
|
|
|
|
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65c00000 0xcd00>;
|
|
|
|
|
interrupt-names = "host", "peripheral";
|
|
|
|
|
interrupts = <0 137 4>, <0 138 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
|
|
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
|
|
|
clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
|
|
|
|
|
resets = <&usb1_rst 15>;
|
|
|
|
|
phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
|
|
|
|
|
<&usb1_ssphy0>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-glue@65d00000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-dwc3-glue",
|
|
|
|
|
"simple-mfd";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x65d00000 0x400>;
|
|
|
|
|
|
|
|
|
|
usb1_rst: reset@0 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-reset";
|
|
|
|
|
reg = <0x0 0x4>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 13>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 13>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_vbus0: regulator@100 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
|
|
|
|
reg = <0x100 0x10>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 13>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 13>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_vbus1: regulator@110 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-regulator";
|
|
|
|
|
reg = <0x110 0x10>;
|
|
|
|
|
clock-names = "link";
|
|
|
|
|
clocks = <&sys_clk 13>;
|
|
|
|
|
reset-names = "link";
|
|
|
|
|
resets = <&sys_rst 13>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_hsphy0: hs-phy@200 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
|
|
|
|
reg = <0x200 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy", "phy-ext";
|
|
|
|
|
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
|
|
|
|
<&sys_clk 14>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 13>, <&sys_rst 20>;
|
|
|
|
|
vbus-supply = <&usb1_vbus0>;
|
|
|
|
|
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
|
|
|
|
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
|
|
|
|
<&usb_hs_i2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_hsphy1: hs-phy@210 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
|
|
|
|
reg = <0x210 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy", "phy-ext";
|
|
|
|
|
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
|
|
|
|
<&sys_clk 14>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 13>, <&sys_rst 20>;
|
|
|
|
|
vbus-supply = <&usb1_vbus1>;
|
|
|
|
|
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
|
|
|
|
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
|
|
|
|
<&usb_hs_i2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_ssphy0: ss-phy@300 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
|
|
|
|
reg = <0x300 0x10>;
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
clock-names = "link", "phy", "phy-ext";
|
|
|
|
|
clocks = <&sys_clk 13>, <&sys_clk 21>,
|
|
|
|
|
<&sys_clk 14>;
|
|
|
|
|
reset-names = "link", "phy";
|
|
|
|
|
resets = <&sys_rst 13>, <&sys_rst 21>;
|
|
|
|
|
vbus-supply = <&usb1_vbus0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* FIXME: U-Boot own node */
|
2017-08-29 03:20:53 +00:00
|
|
|
usb1: usb@65d00000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-dwc3";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x65d00000 0x1000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
|
|
|
|
dwc3@65c00000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x65c00000 0x10000>;
|
|
|
|
|
interrupts = <0 137 4>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
tx-fifo-resize;
|
|
|
|
|
};
|
2017-01-21 09:05:30 +00:00
|
|
|
};
|
|
|
|
|
|
2019-04-12 09:55:50 +00:00
|
|
|
pcie: pcie@66000000 {
|
|
|
|
|
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg-names = "dbi", "link", "config";
|
|
|
|
|
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
|
|
|
|
|
<0x2fff0000 0x10000>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
clocks = <&sys_clk 24>;
|
|
|
|
|
resets = <&sys_rst 24>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
num-viewport = <1>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
ranges =
|
|
|
|
|
/* downstream I/O */
|
|
|
|
|
<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
|
|
|
|
|
/* non-prefetchable memory */
|
|
|
|
|
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-names = "dma", "msi";
|
|
|
|
|
interrupts = <0 224 4>, <0 225 4>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
|
|
|
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
|
|
|
|
|
<0 0 0 2 &pcie_intc 1>, /* INTB */
|
|
|
|
|
<0 0 0 3 &pcie_intc 2>, /* INTC */
|
|
|
|
|
<0 0 0 4 &pcie_intc 3>; /* INTD */
|
|
|
|
|
phy-names = "pcie-phy";
|
|
|
|
|
phys = <&pcie_phy>;
|
|
|
|
|
|
|
|
|
|
pcie_intc: legacy-interrupt-controller {
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <0 226 4>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie_phy: phy@66038000 {
|
|
|
|
|
compatible = "socionext,uniphier-pxs3-pcie-phy";
|
|
|
|
|
reg = <0x66038000 0x4000>;
|
|
|
|
|
#phy-cells = <0>;
|
2020-08-04 05:41:09 +00:00
|
|
|
clock-names = "link";
|
2019-04-12 09:55:50 +00:00
|
|
|
clocks = <&sys_clk 24>;
|
2020-08-04 05:41:09 +00:00
|
|
|
reset-names = "link";
|
2019-04-12 09:55:50 +00:00
|
|
|
resets = <&sys_rst 24>;
|
|
|
|
|
socionext,syscon = <&soc_glue>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-02-28 12:57:19 +00:00
|
|
|
nand: nand-controller@68000000 {
|
2017-08-29 03:20:53 +00:00
|
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
2017-01-21 09:05:30 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
reg-names = "nand_data", "denali_reg";
|
|
|
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
|
|
|
interrupts = <0 65 4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_nand>;
|
2018-12-19 11:03:21 +00:00
|
|
|
clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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2020-02-28 12:57:20 +00:00
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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2017-01-21 09:05:30 +00:00
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};
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};
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};
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2017-08-29 03:20:53 +00:00
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#include "uniphier-pinctrl.dtsi"
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