2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2008-01-16 06:38:05 +00:00
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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2020-05-10 17:40:09 +00:00
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#include <linux/stringify.h>
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2008-01-16 06:38:05 +00:00
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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2009-06-09 20:25:30 +00:00
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#define CONFIG_HWCONFIG
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2008-02-08 19:15:55 +00:00
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/*
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* On-board devices
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*/
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#define CONFIG_VSC7385_ENET
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2008-10-16 13:01:15 +00:00
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/* System performance - define the value i.e. CONFIG_SYS_XXX
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2008-01-16 06:38:05 +00:00
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*/
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/* System Clock Configuration Register */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
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2008-01-16 06:38:05 +00:00
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/*
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* System IO Config
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_SICRH 0x08200000
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#define CONFIG_SYS_SICRL 0x00000000
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2008-01-16 06:38:05 +00:00
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/*
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* Output Buffer Impedance
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_OBIR 0x30100000
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2008-01-16 06:38:05 +00:00
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2008-02-08 19:15:55 +00:00
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/*
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* Device configurations
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*/
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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2008-01-16 06:38:05 +00:00
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/*
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* DDR Setup
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*/
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2019-01-21 08:18:15 +00:00
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
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2008-01-16 06:38:05 +00:00
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#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
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/*
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* Manually set up DDR parameters
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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2011-10-12 04:57:29 +00:00
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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2008-01-16 06:38:05 +00:00
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00260802 */ /* DDR400 */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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2008-01-16 06:38:05 +00:00
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| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (7 << TIMING_CFG1_CASLAT_SHIFT) \
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| (13 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3937d322 */
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2011-10-12 04:57:29 +00:00
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#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (5 << TIMING_CFG2_CPO_SHIFT) \
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| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x02984cc8 */
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2008-01-16 06:38:05 +00:00
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2009-08-21 21:33:15 +00:00
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#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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2008-01-16 06:38:05 +00:00
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/* 0x06090100 */
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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2011-10-12 04:57:29 +00:00
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| SDRAM_CFG_SDRAM_TYPE_DDR2)
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2011-10-12 04:57:19 +00:00
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/* 0x43000000 */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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2009-08-21 21:33:15 +00:00
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#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
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2011-10-12 04:57:19 +00:00
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| (0x0442 << SDRAM_MODE_SD_SHIFT))
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/* 0x04400442 */ /* DDR400 */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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2008-01-16 06:38:05 +00:00
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/*
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* Memory test
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*/
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2008-10-16 13:01:15 +00:00
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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2008-01-16 06:38:05 +00:00
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/*
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* The reserved memory
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*/
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2010-10-07 19:51:12 +00:00
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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2008-01-16 06:38:05 +00:00
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#else
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2008-10-16 13:01:15 +00:00
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#undef CONFIG_SYS_RAMBOOT
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2008-01-16 06:38:05 +00:00
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#endif
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2016-07-08 03:25:14 +00:00
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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2008-01-16 06:38:05 +00:00
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/*
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* Initial RAM Base Address Setup
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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2010-10-26 11:32:32 +00:00
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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2008-01-16 06:38:05 +00:00
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/*
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* FLASH on the Local Bus
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
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2008-01-16 06:38:05 +00:00
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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2008-01-16 06:38:05 +00:00
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2008-03-24 14:40:23 +00:00
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/*
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* NAND Flash on the Local Bus
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*/
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2011-10-12 04:57:30 +00:00
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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2019-01-21 08:18:01 +00:00
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2008-02-08 19:15:55 +00:00
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/* Vitesse 7385 */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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2008-01-16 06:38:05 +00:00
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/*
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* Serial Port
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*/
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_BAUDRATE_TABLE \
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2011-10-12 04:57:19 +00:00
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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2008-01-16 06:38:05 +00:00
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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2008-01-16 06:38:05 +00:00
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2008-03-24 14:40:43 +00:00
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/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_FSL_SERDES2 0xe3100
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2008-01-16 06:38:05 +00:00
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/* I2C */
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2012-10-24 11:48:22 +00:00
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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2008-01-16 06:38:05 +00:00
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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2008-01-16 06:38:05 +00:00
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
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#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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2008-01-16 06:38:05 +00:00
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2009-02-19 15:20:52 +00:00
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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2008-01-16 06:38:05 +00:00
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#ifdef CONFIG_PCI
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/*
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* TSEC
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*/
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2008-02-08 19:15:55 +00:00
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#ifdef CONFIG_TSEC_ENET
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2008-01-16 06:38:05 +00:00
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2008-02-08 19:15:55 +00:00
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#define CONFIG_GMII /* MII PHY management */
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#define CONFIG_TSEC1
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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2008-01-16 06:38:05 +00:00
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#define CONFIG_TSEC1_NAME "TSEC0"
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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2008-01-16 06:38:05 +00:00
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#define TSEC1_PHY_ADDR 2
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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2008-02-08 19:15:55 +00:00
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#endif
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2008-01-16 06:38:05 +00:00
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2008-02-08 19:15:55 +00:00
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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2008-02-08 19:15:55 +00:00
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#define TSEC2_PHY_ADDR 0x1c
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_PHYIDX 0
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#endif
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2008-01-16 06:38:05 +00:00
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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2008-02-08 19:15:55 +00:00
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#endif
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2008-03-28 19:31:23 +00:00
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/*
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* SATA
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*/
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#define CONFIG_SATA1
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_SATA1_OFFSET 0x18000
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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2008-03-28 19:31:23 +00:00
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#define CONFIG_SATA2
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_SATA2_OFFSET 0x19000
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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2008-03-28 19:31:23 +00:00
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#ifdef CONFIG_FSL_SATA
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#define CONFIG_LBA48
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#endif
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2008-01-16 06:38:05 +00:00
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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2008-10-16 13:01:15 +00:00
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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2008-01-16 06:38:05 +00:00
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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2009-06-09 20:25:30 +00:00
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#ifdef CONFIG_MMC
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2011-01-04 09:23:05 +00:00
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#define CONFIG_FSL_ESDHC_PIN_MUX
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2009-06-09 20:25:30 +00:00
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
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#endif
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2008-01-16 06:38:05 +00:00
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/*
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* Miscellaneous configurable options
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*/
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/*
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* For booting Linux, the board info and command line data
|
2010-09-10 22:42:32 +00:00
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* have to be in the first 256 MB of memory, since this is
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2008-01-16 06:38:05 +00:00
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* the maximum mapped by the Linux kernel during initialization.
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*/
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2011-10-12 04:57:19 +00:00
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
2016-07-08 03:25:15 +00:00
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
2008-01-16 06:38:05 +00:00
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/*
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* Environment Configuration
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*/
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|
2008-03-14 20:20:18 +00:00
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|
#define CONFIG_HAS_FSL_DR_USB
|
2014-10-20 11:01:01 +00:00
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|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
2008-03-14 20:20:18 +00:00
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|
2011-10-12 04:57:19 +00:00
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#define CONFIG_NETDEV "eth1"
|
2008-01-16 06:38:05 +00:00
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|
2018-03-28 12:38:20 +00:00
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#define CONFIG_HOSTNAME "mpc837x_rdb"
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2011-10-13 13:03:47 +00:00
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#define CONFIG_ROOTPATH "/nfsroot"
|
2011-10-12 04:57:19 +00:00
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#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
|
2011-10-13 13:03:48 +00:00
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|
#define CONFIG_BOOTFILE "uImage"
|
2011-10-12 04:57:19 +00:00
|
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/* U-Boot image on TFTP server */
|
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|
|
#define CONFIG_UBOOTPATH "u-boot.bin"
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|
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#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
|
2008-01-16 06:38:05 +00:00
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|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
2011-10-12 04:57:19 +00:00
|
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|
"netdev=" CONFIG_NETDEV "\0" \
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|
"uboot=" CONFIG_UBOOTPATH "\0" \
|
2008-01-16 06:38:05 +00:00
|
|
|
"tftpflash=tftp $loadaddr $uboot;" \
|
2012-09-23 15:41:24 +00:00
|
|
|
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
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|
|
" +$filesize; " \
|
|
|
|
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
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|
|
" +$filesize; " \
|
|
|
|
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize; " \
|
|
|
|
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize\0" \
|
2009-08-21 21:34:38 +00:00
|
|
|
"fdtaddr=780000\0" \
|
2011-10-12 04:57:19 +00:00
|
|
|
"fdtfile=" CONFIG_FDTFILE "\0" \
|
2008-01-16 06:38:05 +00:00
|
|
|
"ramdiskaddr=1000000\0" \
|
2011-10-12 04:57:19 +00:00
|
|
|
"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
|
2008-01-16 06:38:05 +00:00
|
|
|
"console=ttyS0\0" \
|
|
|
|
"setbootargs=setenv bootargs " \
|
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
|
|
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
2011-10-12 04:57:19 +00:00
|
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
|
|
"$netdev:off " \
|
2008-01-16 06:38:05 +00:00
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
|
|
|
|
|
|
|
#endif /* __CONFIG_H */
|