2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2013-07-29 18:15:16 +00:00
|
|
|
/*
|
2015-09-02 06:09:45 +00:00
|
|
|
* (C) Copyright 2013 Xilinx, Inc.
|
2015-06-26 19:21:31 +00:00
|
|
|
* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
|
2013-07-29 18:15:16 +00:00
|
|
|
*
|
|
|
|
* Xilinx Zynq PS SPI controller driver (master mode only)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2015-06-26 19:21:31 +00:00
|
|
|
#include <dm.h>
|
2020-02-04 12:47:44 +00:00
|
|
|
#include <dm/device_compat.h>
|
2020-05-10 17:40:05 +00:00
|
|
|
#include <log.h>
|
2013-07-29 18:15:16 +00:00
|
|
|
#include <malloc.h>
|
|
|
|
#include <spi.h>
|
2019-11-14 19:57:30 +00:00
|
|
|
#include <time.h>
|
2020-02-04 12:47:44 +00:00
|
|
|
#include <clk.h>
|
2013-07-29 18:15:16 +00:00
|
|
|
#include <asm/io.h>
|
2020-05-10 17:40:13 +00:00
|
|
|
#include <linux/bitops.h>
|
2020-05-10 17:40:11 +00:00
|
|
|
#include <linux/delay.h>
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2015-06-26 19:21:34 +00:00
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2013-07-29 18:15:16 +00:00
|
|
|
/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
|
2015-10-22 15:10:16 +00:00
|
|
|
#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
|
|
|
|
#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
|
2015-10-22 15:36:37 +00:00
|
|
|
#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
|
|
|
|
#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
|
2015-10-22 15:10:16 +00:00
|
|
|
#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
|
|
|
|
#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
|
|
|
|
#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
|
|
|
|
#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
|
|
|
|
#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
|
2015-10-22 15:36:37 +00:00
|
|
|
#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
|
2015-10-22 15:10:16 +00:00
|
|
|
#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2015-08-17 12:55:03 +00:00
|
|
|
#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
|
|
|
|
#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
|
|
|
|
#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
|
|
|
|
|
2013-07-29 18:15:16 +00:00
|
|
|
#define ZYNQ_SPI_FIFO_DEPTH 128
|
2020-05-18 07:11:00 +00:00
|
|
|
#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* zynq spi register set */
|
|
|
|
struct zynq_spi_regs {
|
|
|
|
u32 cr; /* 0x00 */
|
|
|
|
u32 isr; /* 0x04 */
|
|
|
|
u32 ier; /* 0x08 */
|
|
|
|
u32 idr; /* 0x0C */
|
|
|
|
u32 imr; /* 0x10 */
|
|
|
|
u32 enr; /* 0x14 */
|
|
|
|
u32 dr; /* 0x18 */
|
|
|
|
u32 txdr; /* 0x1C */
|
|
|
|
u32 rxdr; /* 0x20 */
|
|
|
|
};
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
|
|
|
|
/* zynq spi platform data */
|
2020-12-03 23:55:23 +00:00
|
|
|
struct zynq_spi_plat {
|
2015-06-26 19:21:31 +00:00
|
|
|
struct zynq_spi_regs *regs;
|
|
|
|
u32 frequency; /* input frequency */
|
2013-07-29 18:15:16 +00:00
|
|
|
u32 speed_hz;
|
2016-12-08 20:11:09 +00:00
|
|
|
uint deactivate_delay_us; /* Delay to wait after deactivate */
|
|
|
|
uint activate_delay_us; /* Delay to wait after activate */
|
2013-07-29 18:15:16 +00:00
|
|
|
};
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
/* zynq spi priv */
|
|
|
|
struct zynq_spi_priv {
|
|
|
|
struct zynq_spi_regs *regs;
|
2015-08-17 13:01:39 +00:00
|
|
|
u8 cs;
|
2015-06-26 19:21:31 +00:00
|
|
|
u8 mode;
|
2016-12-08 20:11:09 +00:00
|
|
|
ulong last_transaction_us; /* Time of last transaction end */
|
2015-06-26 19:21:31 +00:00
|
|
|
u8 fifo_depth;
|
|
|
|
u32 freq; /* required frequency */
|
|
|
|
};
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2020-12-03 23:55:21 +00:00
|
|
|
static int zynq_spi_of_to_plat(struct udevice *bus)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynq_spi_plat *plat = dev_get_plat(bus);
|
2015-06-26 19:21:34 +00:00
|
|
|
const void *blob = gd->fdt_blob;
|
2017-01-17 23:52:55 +00:00
|
|
|
int node = dev_of_offset(bus);
|
2015-06-26 19:21:34 +00:00
|
|
|
|
2020-07-17 05:36:46 +00:00
|
|
|
plat->regs = dev_read_addr_ptr(bus);
|
2015-06-26 19:21:31 +00:00
|
|
|
|
2016-12-08 20:11:09 +00:00
|
|
|
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
|
|
|
"spi-deactivate-delay", 0);
|
|
|
|
plat->activate_delay_us = fdtdec_get_int(blob, node,
|
|
|
|
"spi-activate-delay", 0);
|
2015-06-26 19:21:34 +00:00
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
|
|
|
|
{
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2013-07-29 18:15:16 +00:00
|
|
|
u32 confr;
|
|
|
|
|
|
|
|
/* Disable SPI */
|
2016-09-01 10:51:27 +00:00
|
|
|
confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
|
|
|
|
writel(~confr, ®s->enr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* Disable Interrupts */
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* Clear RX FIFO */
|
2015-06-26 19:21:31 +00:00
|
|
|
while (readl(®s->isr) &
|
2013-07-29 18:15:16 +00:00
|
|
|
ZYNQ_SPI_IXR_RXNEMPTY_MASK)
|
2015-06-26 19:21:31 +00:00
|
|
|
readl(®s->rxdr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* Clear Interrupts */
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* Manual slave select and Auto start */
|
|
|
|
confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
|
|
|
|
ZYNQ_SPI_CR_MSTREN_MASK;
|
|
|
|
confr &= ~ZYNQ_SPI_CR_MSA_MASK;
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(confr, ®s->cr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
/* Enable SPI */
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
static int zynq_spi_probe(struct udevice *bus)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2020-12-03 23:55:23 +00:00
|
|
|
struct zynq_spi_plat *plat = dev_get_plat(bus);
|
2015-06-26 19:21:31 +00:00
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
2020-02-04 12:47:44 +00:00
|
|
|
struct clk clk;
|
|
|
|
unsigned long clock;
|
|
|
|
int ret;
|
2015-06-26 19:21:31 +00:00
|
|
|
|
|
|
|
priv->regs = plat->regs;
|
|
|
|
priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
|
|
|
|
|
2020-02-04 12:47:44 +00:00
|
|
|
ret = clk_get_by_name(bus, "ref_clk", &clk);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(bus, "failed to get clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
clock = clk_get_rate(&clk);
|
|
|
|
if (IS_ERR_VALUE(clock)) {
|
|
|
|
dev_err(bus, "failed to get rate\n");
|
|
|
|
return clock;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_enable(&clk);
|
|
|
|
if (ret && ret != -ENOSYS) {
|
|
|
|
dev_err(bus, "failed to enable clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
/* init the zynq spi hw */
|
|
|
|
zynq_spi_init_hw(priv);
|
|
|
|
|
2020-02-04 12:47:44 +00:00
|
|
|
plat->frequency = clock;
|
|
|
|
plat->speed_hz = plat->frequency / 2;
|
|
|
|
|
|
|
|
debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
return 0;
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
2015-08-17 13:01:39 +00:00
|
|
|
static void spi_cs_activate(struct udevice *dev)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2015-06-26 19:21:31 +00:00
|
|
|
struct udevice *bus = dev->parent;
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynq_spi_plat *plat = dev_get_plat(bus);
|
2015-06-26 19:21:31 +00:00
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2013-07-29 18:15:16 +00:00
|
|
|
u32 cr;
|
|
|
|
|
2016-12-08 20:11:09 +00:00
|
|
|
/* If it's too soon to do another transaction, wait */
|
|
|
|
if (plat->deactivate_delay_us && priv->last_transaction_us) {
|
|
|
|
ulong delay_us; /* The delay completed so far */
|
|
|
|
delay_us = timer_get_us() - priv->last_transaction_us;
|
|
|
|
if (delay_us < plat->deactivate_delay_us)
|
|
|
|
udelay(plat->deactivate_delay_us - delay_us);
|
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
|
|
|
|
cr = readl(®s->cr);
|
2013-07-29 18:15:16 +00:00
|
|
|
/*
|
|
|
|
* CS cal logic: CS[13:10]
|
|
|
|
* xxx0 - cs0
|
|
|
|
* xx01 - cs1
|
|
|
|
* x011 - cs2
|
|
|
|
*/
|
2015-08-17 13:01:39 +00:00
|
|
|
cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(cr, ®s->cr);
|
2016-12-08 20:11:09 +00:00
|
|
|
|
|
|
|
if (plat->activate_delay_us)
|
|
|
|
udelay(plat->activate_delay_us);
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
static void spi_cs_deactivate(struct udevice *dev)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2015-06-26 19:21:31 +00:00
|
|
|
struct udevice *bus = dev->parent;
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynq_spi_plat *plat = dev_get_plat(bus);
|
2015-06-26 19:21:31 +00:00
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
|
2016-12-08 20:11:09 +00:00
|
|
|
|
|
|
|
/* Remember time of this transaction so we can honour the bus delay */
|
|
|
|
if (plat->deactivate_delay_us)
|
|
|
|
priv->last_transaction_us = timer_get_us();
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
static int zynq_spi_claim_bus(struct udevice *dev)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2015-06-26 19:21:31 +00:00
|
|
|
struct udevice *bus = dev->parent;
|
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
return 0;
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
static int zynq_spi_release_bus(struct udevice *dev)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2015-06-26 19:21:31 +00:00
|
|
|
struct udevice *bus = dev->parent;
|
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2016-09-01 10:51:27 +00:00
|
|
|
u32 confr;
|
2013-07-29 18:15:16 +00:00
|
|
|
|
2016-09-01 10:51:27 +00:00
|
|
|
confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
|
|
|
|
writel(~confr, ®s->enr);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-06-26 19:21:31 +00:00
|
|
|
static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
|
|
const void *dout, void *din, unsigned long flags)
|
2013-07-29 18:15:16 +00:00
|
|
|
{
|
2015-06-26 19:21:31 +00:00
|
|
|
struct udevice *bus = dev->parent;
|
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
2020-12-03 23:55:23 +00:00
|
|
|
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
|
2013-07-29 18:15:16 +00:00
|
|
|
u32 len = bitlen / 8;
|
|
|
|
u32 tx_len = len, rx_len = len, tx_tvl;
|
|
|
|
const u8 *tx_buf = dout;
|
|
|
|
u8 *rx_buf = din, buf;
|
|
|
|
u32 ts, status;
|
|
|
|
|
|
|
|
debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
|
2020-12-17 04:20:07 +00:00
|
|
|
dev_seq(bus), slave_plat->cs, bitlen, len, flags);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
if (bitlen % 8) {
|
|
|
|
debug("spi_xfer: Non byte aligned SPI transfer\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2015-08-17 13:01:39 +00:00
|
|
|
priv->cs = slave_plat->cs;
|
2013-07-29 18:15:16 +00:00
|
|
|
if (flags & SPI_XFER_BEGIN)
|
2015-08-17 13:01:39 +00:00
|
|
|
spi_cs_activate(dev);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
while (rx_len > 0) {
|
|
|
|
/* Write the data into TX FIFO - tx threshold is fifo_depth */
|
|
|
|
tx_tvl = 0;
|
2015-06-26 19:21:31 +00:00
|
|
|
while ((tx_tvl < priv->fifo_depth) && tx_len) {
|
2013-07-29 18:15:16 +00:00
|
|
|
if (tx_buf)
|
|
|
|
buf = *tx_buf++;
|
|
|
|
else
|
|
|
|
buf = 0;
|
2015-06-26 19:21:31 +00:00
|
|
|
writel(buf, ®s->txdr);
|
2013-07-29 18:15:16 +00:00
|
|
|
tx_len--;
|
|
|
|
tx_tvl++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check TX FIFO completion */
|
|
|
|
ts = get_timer(0);
|
2015-06-26 19:21:31 +00:00
|
|
|
status = readl(®s->isr);
|
2013-07-29 18:15:16 +00:00
|
|
|
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
|
2020-05-18 07:11:00 +00:00
|
|
|
if (get_timer(ts) > ZYNQ_SPI_WAIT) {
|
2013-07-29 18:15:16 +00:00
|
|
|
printf("spi_xfer: Timeout! TX FIFO not full\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2015-06-26 19:21:31 +00:00
|
|
|
status = readl(®s->isr);
|
2013-07-29 18:15:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the data from RX FIFO */
|
2015-06-26 19:21:31 +00:00
|
|
|
status = readl(®s->isr);
|
2016-07-30 21:28:24 +00:00
|
|
|
while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
|
2015-06-26 19:21:31 +00:00
|
|
|
buf = readl(®s->rxdr);
|
2013-07-29 18:15:16 +00:00
|
|
|
if (rx_buf)
|
|
|
|
*rx_buf++ = buf;
|
2015-06-26 19:21:31 +00:00
|
|
|
status = readl(®s->isr);
|
2013-07-29 18:15:16 +00:00
|
|
|
rx_len--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (flags & SPI_XFER_END)
|
2015-06-26 19:21:31 +00:00
|
|
|
spi_cs_deactivate(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynq_spi_set_speed(struct udevice *bus, uint speed)
|
|
|
|
{
|
2020-12-23 02:30:28 +00:00
|
|
|
struct zynq_spi_plat *plat = dev_get_plat(bus);
|
2015-06-26 19:21:31 +00:00
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
|
|
|
uint32_t confr;
|
|
|
|
u8 baud_rate_val = 0;
|
|
|
|
|
|
|
|
if (speed > plat->frequency)
|
|
|
|
speed = plat->frequency;
|
|
|
|
|
|
|
|
/* Set the clock frequency */
|
|
|
|
confr = readl(®s->cr);
|
|
|
|
if (speed == 0) {
|
|
|
|
/* Set baudrate x8, if the freq is 0 */
|
|
|
|
baud_rate_val = 0x2;
|
|
|
|
} else if (plat->speed_hz != speed) {
|
2015-08-17 12:55:03 +00:00
|
|
|
while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
|
2015-06-26 19:21:31 +00:00
|
|
|
((plat->frequency /
|
|
|
|
(2 << baud_rate_val)) > speed))
|
|
|
|
baud_rate_val++;
|
|
|
|
plat->speed_hz = speed / (2 << baud_rate_val);
|
|
|
|
}
|
2015-08-17 12:57:47 +00:00
|
|
|
confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
|
2015-08-17 12:55:03 +00:00
|
|
|
confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
|
2015-06-26 19:21:31 +00:00
|
|
|
|
|
|
|
writel(confr, ®s->cr);
|
|
|
|
priv->freq = speed;
|
|
|
|
|
2015-09-07 20:08:50 +00:00
|
|
|
debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
|
|
|
|
priv->regs, priv->freq);
|
2015-06-26 19:21:31 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int zynq_spi_set_mode(struct udevice *bus, uint mode)
|
|
|
|
{
|
|
|
|
struct zynq_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
struct zynq_spi_regs *regs = priv->regs;
|
|
|
|
uint32_t confr;
|
|
|
|
|
|
|
|
/* Set the SPI Clock phase and polarities */
|
|
|
|
confr = readl(®s->cr);
|
|
|
|
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
|
|
|
|
|
2015-09-07 20:08:50 +00:00
|
|
|
if (mode & SPI_CPHA)
|
2015-06-26 19:21:31 +00:00
|
|
|
confr |= ZYNQ_SPI_CR_CPHA_MASK;
|
2015-09-07 20:08:50 +00:00
|
|
|
if (mode & SPI_CPOL)
|
2015-06-26 19:21:31 +00:00
|
|
|
confr |= ZYNQ_SPI_CR_CPOL_MASK;
|
|
|
|
|
|
|
|
writel(confr, ®s->cr);
|
|
|
|
priv->mode = mode;
|
|
|
|
|
|
|
|
debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
|
2013-07-29 18:15:16 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2015-06-26 19:21:31 +00:00
|
|
|
|
|
|
|
static const struct dm_spi_ops zynq_spi_ops = {
|
|
|
|
.claim_bus = zynq_spi_claim_bus,
|
|
|
|
.release_bus = zynq_spi_release_bus,
|
|
|
|
.xfer = zynq_spi_xfer,
|
|
|
|
.set_speed = zynq_spi_set_speed,
|
|
|
|
.set_mode = zynq_spi_set_mode,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id zynq_spi_ids[] = {
|
2015-07-22 08:47:33 +00:00
|
|
|
{ .compatible = "xlnx,zynq-spi-r1p6" },
|
2015-12-07 12:06:54 +00:00
|
|
|
{ .compatible = "cdns,spi-r1p6" },
|
2015-06-26 19:21:31 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(zynq_spi) = {
|
|
|
|
.name = "zynq_spi",
|
|
|
|
.id = UCLASS_SPI,
|
|
|
|
.of_match = zynq_spi_ids,
|
|
|
|
.ops = &zynq_spi_ops,
|
2020-12-03 23:55:21 +00:00
|
|
|
.of_to_plat = zynq_spi_of_to_plat,
|
2020-12-03 23:55:23 +00:00
|
|
|
.plat_auto = sizeof(struct zynq_spi_plat),
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct zynq_spi_priv),
|
2015-06-26 19:21:31 +00:00
|
|
|
.probe = zynq_spi_probe,
|
|
|
|
};
|