2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-07-09 20:44:48 +00:00
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/*
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* Common configuration header file for all Keystone II EVM platforms
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef __CONFIG_KS2_EVM_H
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#define __CONFIG_KS2_EVM_H
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/* U-Boot Build Configuration */
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/* SoC Configuration */
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/* Memory Configuration */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
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2022-12-04 15:04:51 +00:00
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#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
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2014-07-09 20:44:48 +00:00
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2015-09-19 09:30:17 +00:00
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#ifdef CONFIG_SYS_MALLOC_F_LEN
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#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
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#else
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#define SPL_MALLOC_F_SIZE 0
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#endif
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2014-07-09 20:44:48 +00:00
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/* SPL SPI Loader Configuration */
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2017-02-03 12:31:46 +00:00
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#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
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2014-07-09 20:44:48 +00:00
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2017-03-13 13:04:26 +00:00
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/* SRAM scratch space entries */
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2022-05-19 19:09:22 +00:00
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#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc
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2017-03-13 13:04:26 +00:00
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR)
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
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#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
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2014-07-09 20:44:48 +00:00
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/* UART Configuration */
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE
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#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE
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2014-07-09 20:44:48 +00:00
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2015-09-19 10:56:41 +00:00
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#ifndef CONFIG_SOC_K2G
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
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2015-09-19 10:56:41 +00:00
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#else
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
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2015-09-19 10:56:41 +00:00
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#endif
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2014-07-09 20:44:48 +00:00
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/* SPI Configuration */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
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2014-07-09 20:44:48 +00:00
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2014-09-29 19:17:22 +00:00
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/* Keystone net */
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2022-12-04 15:04:26 +00:00
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#define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
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2022-12-04 15:04:27 +00:00
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#define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE
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2022-12-04 15:04:30 +00:00
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#define CFG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
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2022-12-04 15:04:29 +00:00
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#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
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2022-12-04 15:04:28 +00:00
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#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
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2014-09-29 19:17:22 +00:00
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2014-07-09 20:44:48 +00:00
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/* EEPROM definitions */
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/* NAND Configuration */
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_MASK_CLE 0x4000
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#define CFG_SYS_NAND_MASK_ALE 0x2000
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#define CFG_SYS_NAND_CS 2
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2014-07-09 20:44:48 +00:00
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_LARGEPAGE
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#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
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2014-07-09 20:44:48 +00:00
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2018-12-04 10:13:01 +00:00
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2014-07-09 20:44:48 +00:00
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/* U-Boot general configuration */
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/* EDMA3 */
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2015-07-22 23:05:45 +00:00
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/* Now for the remaining common defines */
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#include <configs/ti_armv7_common.h>
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2014-07-09 20:44:48 +00:00
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/* we may include files below only after all above definitions */
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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2015-09-19 10:56:41 +00:00
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#ifndef CONFIG_SOC_K2G
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
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2015-09-19 10:56:41 +00:00
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#else
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk)
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2015-09-19 10:56:41 +00:00
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#endif
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2014-07-09 20:44:48 +00:00
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#endif /* __CONFIG_KS2_EVM_H */
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