2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2016-02-03 02:16:48 +00:00
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/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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2019-04-03 05:37:40 +00:00
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#include <dm.h>
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#include <wdt.h>
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2016-02-03 02:16:48 +00:00
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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2019-04-03 05:37:40 +00:00
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#include <asm/arch/at91_wdt.h>
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2016-02-03 02:16:48 +00:00
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2016-02-02 03:11:51 +00:00
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#define EN_UPLL_TIMEOUT 500
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2019-04-03 05:37:40 +00:00
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static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL;
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2016-02-03 02:16:48 +00:00
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void at91_periph_clk_enable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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#ifdef CPU_HAS_PCR
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u32 regval;
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u32 div_value;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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writel(id, &pmc->pcr);
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div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
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regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
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writel(regval, &pmc->pcr);
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#else
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writel(0x01 << id, &pmc->pcer);
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#endif
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}
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void at91_periph_clk_disable(int id)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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#ifdef CPU_HAS_PCR
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u32 regval;
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if (id > AT91_PMC_PCR_PID_MASK)
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return;
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regval = AT91_PMC_PCR_CMD_WRITE | id;
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writel(regval, &pmc->pcr);
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#else
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writel(0x01 << id, &pmc->pcdr);
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#endif
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}
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void at91_system_clk_enable(int sys_clk)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(sys_clk, &pmc->scer);
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}
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void at91_system_clk_disable(int sys_clk)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(sys_clk, &pmc->scdr);
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}
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2016-02-02 03:11:51 +00:00
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int at91_upll_clk_enable(void)
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{
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struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
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ulong start_time, tmp_time;
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if ((readl(&pmc->uckr) & AT91_PMC_UPLLEN) == AT91_PMC_UPLLEN)
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return 0;
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start_time = get_timer(0);
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writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
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while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) {
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tmp_time = get_timer(0);
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if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
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printf("ERROR: failed to enable UPLL\n");
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return -1;
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}
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}
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return 0;
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}
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int at91_upll_clk_disable(void)
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{
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struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
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ulong start_time, tmp_time;
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start_time = get_timer(0);
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writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr);
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while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) {
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tmp_time = get_timer(0);
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if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) {
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printf("ERROR: failed to stop UPLL\n");
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return -1;
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}
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}
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return 0;
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}
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void at91_usb_clk_init(u32 value)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(value, &pmc->usb);
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}
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2016-02-02 04:46:12 +00:00
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void at91_pllicpr_init(u32 icpr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(icpr, &pmc->pllicpr);
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}
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2019-04-03 05:37:40 +00:00
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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static ulong next_reset;
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ulong now;
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if (!watchdog_dev)
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return;
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now = get_timer(0);
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/* Do not reset the watchdog too often */
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if (now > next_reset) {
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next_reset = now + 1000; /* reset every 1000ms */
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wdt_reset(watchdog_dev);
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}
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}
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int arch_early_init_r(void)
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{
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struct at91_wdt_priv *priv;
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/* Init watchdog */
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if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
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debug("Watchdog: Not found by seq!\n");
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
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puts("Watchdog: Not found!\n");
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return 0;
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}
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}
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priv = dev_get_priv(watchdog_dev);
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if (!priv) {
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printf("Watchdog: priv not available!\n");
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return 0;
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}
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wdt_start(watchdog_dev, priv->timeout * 1000, 0);
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printf("Watchdog: Started\n");
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return 0;
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}
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