Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-06 13:14:27 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi

137 lines
3.3 KiB
Text
Raw Normal View History

arm: dts: ti: Add Support for J721E SoC Add initial SoC definition for J721E SoC. Kernel dts posted here: https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/ Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:53 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
&cbass_mcu_wakeup {
dmsc: dmsc@44083000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44083000 0x0 0x1000>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
ti,scan-clocks-from-dt;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x4301c000 0x00 0x178>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
};
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
arm: dts: k3-j721e-mcu: Add MCU domain R5F cluster node The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5 cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:37 +00:00
mcu_r5fss0: r5fss@41000000 {
compatible = "ti,j721e-r5fss";
lockstep-mode = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x41000000 0x00 0x41000000 0x20000>,
<0x41400000 0x00 0x41400000 0x20000>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
mcu_r5fss0_core0: r5f@41000000 {
compatible = "ti,j721e-r5f";
reg = <0x41000000 0x00008000>,
<0x41010000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <250>;
ti,sci-proc-ids = <0x01 0xFF>;
resets = <&k3_reset 250 1>;
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
mcu_r5fss0_core1: r5f@41400000 {
compatible = "ti,j721e-r5f";
reg = <0x41400000 0x00008000>,
<0x41410000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <251>;
ti,sci-proc-ids = <0x02 0xFF>;
resets = <&k3_reset 251 1>;
atcm-enable = <1>;
btcm-enable = <1>;
loczrama = <1>;
};
};
arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not possible to use OSPI0 and HBMC simultaneously as they are muxed within the Flash Subsystem hence disable HBMC by default as keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash instead of OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-23 08:00:02 +00:00
fss: fss@47000000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
hbmc_mux: hbmc-mux {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
reg = <0x0 0x47034000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
assigned-clocks = <&k3_clks 102 0>;
assigned-clock-rates = <250000000>;
};
};
arm: dts: ti: Add Support for J721E SoC Add initial SoC definition for J721E SoC. Kernel dts posted here: https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/ Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:53 +00:00
};
Reference in a new issue Copy permalink