u-boot/arch/riscv/include/asm/syscon.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
 */

#ifndef _ASM_SYSCON_H
#define _ASM_SYSCON_H

/*
 * System controllers in a RISC-V system. These should only be used for
 * identifying IPI controllers. Other devices should use DM to probe.
 */
enum {
	RISCV_NONE,
	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
};

#endif /* _ASM_SYSCON_H */
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:30 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>`
			`*/`

			`#ifndef _ASM_SYSCON_H`
			`#define _ASM_SYSCON_H`

			`/*`
riscv: Rework Andes PLMT as a UCLASS_TIMER driver This converts the PLMT driver from the riscv-specific timer interface to be a DM-based UCLASS_TIMER driver. The clock-frequency/clocks properties are preferred over timebase-frequency for two reasons. First, properties which affect a device should be located near its binding in the device tree. Using timebase-frequency only really makes sense when the cpu itself is the timer device. This is the case when we read the time from a CSR, but not when there is a separate device. Second, it lets the device use the clock subsystem which adds flexibility. If the device is configured for a different clock speed, the timer can adjust itself. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> 2020-09-28 14:52:24 +00:00			`* System controllers in a RISC-V system. These should only be used for`
			`* identifying IPI controllers. Other devices should use DM to probe.`
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:30 +00:00			`*/`
			`enum {`
			`RISCV_NONE,`
			`RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */`
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> 2019-04-02 07:56:39 +00:00			`RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */`
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> 2018-12-12 14:12:30 +00:00			`};`

			`#endif /* _ASM_SYSCON_H */`