mirror of
https://github.com/AsahiLinux/u-boot
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136 lines
2.4 KiB
C
136 lines
2.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/gcr.h>
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#include <asm/armv8/mmu.h>
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#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
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#define SC_CNTCR_ENABLE BIT(0)
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#define SC_CNTCR_HDBG BIT(1)
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#define SC_CNTCR_FREQ0 BIT(8)
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#define SC_CNTCR_FREQ1 BIT(9)
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/* System Counter register map */
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struct sctr_regs {
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u32 cntcr;
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u32 cntsr;
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u32 cntcv1;
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u32 cntcv2;
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u32 resv1[4];
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u32 cntfid0;
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u32 cntfid1;
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u32 cntfid2;
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u32 resv2[1001];
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u32 counterid[1];
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};
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DECLARE_GLOBAL_DATA_PTR;
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int print_cpuinfo(void)
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{
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struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
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unsigned int val;
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unsigned long mpidr_val;
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asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
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val = readl(&gcr->mdlr);
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printf("CPU-%lu: ", mpidr_val & 0x3);
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switch (val) {
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case ARBEL_NPCM845:
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printf("NPCM845 ");
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break;
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case ARBEL_NPCM830:
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printf("NPCM830 ");
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break;
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case ARBEL_NPCM810:
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printf("NPCM810 ");
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break;
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default:
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printf("NPCM8XX ");
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break;
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}
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val = readl(&gcr->pdid);
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switch (val) {
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case ARBEL_Z1:
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printf("Z1 @ ");
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break;
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case ARBEL_A1:
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printf("A1 @ ");
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break;
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default:
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printf("Unknown\n");
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break;
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}
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return 0;
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}
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int arch_cpu_init(void)
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{
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if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
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/* Enable cache to speed up system running */
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if (get_sctlr() & CR_M)
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return 0;
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icache_enable();
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__asm_invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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set_sctlr(get_sctlr() | CR_C);
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}
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return 0;
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}
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static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
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{
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/* DRAM */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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.phys = 0x80000000UL,
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.virt = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = npcm_mem_map;
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int timer_init(void)
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{
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struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
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u32 cntfrq_el0;
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/* Enable system counter */
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__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
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writel(cntfrq_el0, &sctr->cntfid0);
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clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
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SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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return 0;
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}
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