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u-boot/drivers/clk/sunxi/clk_a80.c

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clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Amarula Solutions.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
clk: sunxi: Move header out of arch directory The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 16:48:43 +00:00
#include <clk/sunxi.h>
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
static const struct ccu_clk_gate a80_gates[] = {
clk: sunxi: Add NAND clocks and resets Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-22 22:06:31 +00:00
[CLK_NAND0_0] = GATE(0x400, BIT(31)),
[CLK_NAND0_1] = GATE(0x404, BIT(31)),
[CLK_NAND1_0] = GATE(0x408, BIT(31)),
[CLK_NAND1_1] = GATE(0x40c, BIT(31)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
[CLK_SPI0] = GATE(0x430, BIT(31)),
[CLK_SPI1] = GATE(0x434, BIT(31)),
[CLK_SPI2] = GATE(0x438, BIT(31)),
[CLK_SPI3] = GATE(0x43c, BIT(31)),
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
clk: sunxi: Add NAND clocks and resets Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-22 22:06:31 +00:00
[CLK_BUS_NAND0] = GATE(0x580, BIT(13)),
[CLK_BUS_NAND1] = GATE(0x580, BIT(12)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
clk: sunxi: add PIO bus gate clocks The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-04 21:10:28 +00:00
[CLK_BUS_PIO] = GATE(0x590, BIT(5)),
clk: sunxi: Add support for I2C gates/resets Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:24 +00:00
[CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
[CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
[CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
[CLK_BUS_UART3] = GATE(0x594, BIT(19)),
[CLK_BUS_UART4] = GATE(0x594, BIT(20)),
[CLK_BUS_UART5] = GATE(0x594, BIT(21)),
};
static const struct ccu_reset a80_resets[] = {
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
clk: sunxi: Add NAND clocks and resets Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-22 22:06:31 +00:00
[RST_BUS_NAND0] = RESET(0x5a0, BIT(13)),
[RST_BUS_NAND1] = RESET(0x5a0, BIT(12)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
clk: sunxi: Add support for I2C gates/resets Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:24 +00:00
[RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
[RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
[RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
[RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
[RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
[RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
[RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
[RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
};
sunxi: clk: A80: add MMC clock support The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:10 +00:00
static const struct ccu_clk_gate a80_mmc_gates[] = {
[0] = GATE(0x0, BIT(16)),
[1] = GATE(0x4, BIT(16)),
[2] = GATE(0x8, BIT(16)),
[3] = GATE(0xc, BIT(16)),
};
static const struct ccu_reset a80_mmc_resets[] = {
[0] = GATE(0x0, BIT(18)),
[1] = GATE(0x4, BIT(18)),
[2] = GATE(0x8, BIT(18)),
[3] = GATE(0xc, BIT(18)),
};
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
const struct ccu_desc a80_ccu_desc = {
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
.gates = a80_gates,
.resets = a80_resets,
clk: sunxi: Store the array sizes in the CCU descriptor The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:31 +00:00
.num_gates = ARRAY_SIZE(a80_gates),
.num_resets = ARRAY_SIZE(a80_resets),
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
};
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
const struct ccu_desc a80_mmc_clk_desc = {
sunxi: clk: A80: add MMC clock support The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:10 +00:00
.gates = a80_mmc_gates,
.resets = a80_mmc_resets,
clk: sunxi: Store the array sizes in the CCU descriptor The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:31 +00:00
.num_gates = ARRAY_SIZE(a80_mmc_gates),
.num_resets = ARRAY_SIZE(a80_mmc_resets),
sunxi: clk: A80: add MMC clock support The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:10 +00:00
};
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