Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 23:47:24 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/drivers/phy/Makefile

45 lines
1.9 KiB
Makefile
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
# SPDX-License-Identifier: GPL-2.0+
drivers: phy: add generic PHY framework The PHY framework provides a set of APIs to control a PHY. This API is derived from the linux version of the generic PHY framework. Currently the API supports init(), deinit(), power_on, power_off() and reset(). The framework provides a way to get a reference to a phy from the device-tree. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 09:51:27 +00:00
#
# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
# Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
Makefile: Move phy rules into drivers/phy These don't belong in the drivers Makefile so move them down into the correct place. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup some missing dependencies this exposed] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-11 03:14:23 +00:00
obj-y += allwinner/
obj-y += marvell/
obj-y += rockchip/
obj-y += socionext/
drivers: phy: add generic PHY framework The PHY framework provides a set of APIs to control a PHY. This API is derived from the linux version of the generic PHY framework. Currently the API supports init(), deinit(), power_on, power_off() and reset(). The framework provides a way to get a reference to a phy from the device-tree. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 09:51:27 +00:00
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
phy: add a NO-OP phy driver This driver is used to stub PHY operations in a driver (USB, SATA). This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework and there is no actual PHY harwdare to drive. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-07-24 13:18:15 +00:00
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
phy: dphy: Add configuration helpers The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-29 13:58:58 +00:00
obj-$(CONFIG_MIPI_DPHY_HELPERS) += phy-core-mipi-dphy.o
phy: Add driver for ST-Ericsson AB8500 USB PHY The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-08 18:33:49 +00:00
obj-$(CONFIG_AB8500_USB_PHY) += phy-ab8500-usb.o
phy: add support for bcm6318 usbh phy Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-04 20:11:15 +00:00
obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
phy: add support for bcm6348 usbh phy Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-04 10:18:24 +00:00
obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
phy: add support for bcm6358 usbh phy Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-04 10:19:11 +00:00
obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
phy: add support for bcm6368 usbh phy Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-04 20:10:13 +00:00
obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
phy: add support for stingray PAXB PHY controller Add support for stingray PAXB PHY controller driver. This driver supports maximum 8 PAXB phys using pipemux data. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-02 10:38:12 +00:00
obj-$(CONFIG_BCM_SR_PCIE_PHY) += phy-bcm-sr-pcie.o
dm: test: Add tests for the generic PHY uclass Those tests check: - the ability for a phy-user to get a phy based on its name or its index - the ability of a phy device (provider) to manage multiple ports - the ability to perform operations on the phy (init,deinit,on,off) - the behavior of the uclass when optional operations are not implemented Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 09:51:28 +00:00
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
drivers: phy: add PIPE3 phy driver This phy is found on omap platforms with sata capabilities. Except for the part related to the DM and the PHY framework, the code is basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 09:51:29 +00:00
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
phy: add support for AM654x SERDES Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 can be added later. SERDES in am654x has three input clocks (left input, external reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-01 13:42:58 +00:00
obj-$(CONFIG_AM654_PHY) += phy-ti-am654.o
usb: phy: Add STi USB2 PHY This is the generic phy driver for the picoPHY ports used by USB2/1.1 controllers. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-05 09:04:21 +00:00
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
phy: add driver for Qualcomm IPQ40xx USB PHY Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-10 14:00:04 +00:00
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
phy: rcar: Add R-Car Gen2 PHY driver Add a PHY driver for the R-Car Gen2 which allows configuring the mux connected to the EHCI controllers and USBHS controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-08-05 13:22:19 +00:00
obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
phy: rcar: Add R-Car Gen3 PHY driver Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-02 20:31:47 +00:00
obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o
phy: add support for STM32 usb phy controller This patch adds phy tranceiver driver for STM32 USB PHY Controller (usbphyc) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-27 09:01:55 +00:00
obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
phy: meson: add GXBB PHY driver This adds support for the USB PHY found on Amlogic GXBB SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-18 13:42:54 +00:00
obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o
phy: meson-gxl: remove invalid USB3 PHY driver The registers which are managed by the meson-gxl-usb3 PHY driver are actually "USB control" registers (which are "glue" registers which manage OTG detection and routing of the OTG capable port between the DWC2 peripheral-only controller and the DWC3 host-only controller). Drop the meson-gxl-usb3 PHY driver now that the dwc3-meson-gxl-usb driver supports the USB control registers on GXL and GXM SoCs (these were previously managed by the meson-gxl-usb3 PHY driver). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-10 08:48:15 +00:00
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o
phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY drivers This adds support for the USB PHYs found in the Amlogic G12A SoC Family. The USB2 PHY supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-02-19 14:17:29 +00:00
obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o
phy: Add Amlogic AXG MIPI D-PHY driver The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. This D-PHY depends on a separate analog PHY. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-29 13:59:00 +00:00
obj-$(CONFIG_MESON_AXG_MIPI_DPHY) += meson-axg-mipi-dphy.o
phy: Add Amlogic AXG MIPI PCIe Analog PHY driver The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission and Analog part of the PCIe lines. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-12-29 13:59:01 +00:00
obj-$(CONFIG_MESON_AXG_MIPI_PCIE_ANALOG_PHY) += meson-axg-mipi-pcie-analog.o
phy: db410c: Add MSM USB PHY driver Add a PHY driver for the Qualcomm dragonboard 410c which allows switching on/off and resetting the phy connected to the EHCI controllers and USBHS controller. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-09-21 10:35:47 +00:00
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
phy: Add a new driver for OMAP's USB2 PHYs This drivers supports the USB2 PHY found on omap5 and dra7 SOCs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-11-29 09:57:39 +00:00
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
PHY: Add phy driver for the keystone USB PHY Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-04 10:12:59 +00:00
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
phy: add USB PHY driver for MediaTek MT7620 SoC This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-11-12 08:36:48 +00:00
obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
phy: Add USB PHY driver for the MT76x8 (7628/7688) SoC This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-05 11:44:43 +00:00
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
phy: Add support for phy-da8xx-usb In preparation for supporting the musb driver, this patch adds support for the usb phy associated with the musb driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-10 18:59:09 +00:00
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
phy: mediatek: add MediaTek T-PHY support for PCIe The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-08-22 10:26:50 +00:00
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
phy: nuvoton: add NPCM7xx phy control driver add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-21 09:03:38 +00:00
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-02-21 16:26:21 +00:00
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
phy: zynqmp: Add serdes/psgtr driver Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2022-01-06 08:49:41 +00:00
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
phy: cadence: Add driver for Sierra PHY Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-21 15:58:36 +00:00
obj-y += cadence/
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-21 15:58:38 +00:00
obj-y += ti/
Reference in a new issue Copy permalink