2021-04-25 20:28:00 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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2023-01-26 20:01:32 +00:00
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* Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
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2021-04-25 20:28:00 +00:00
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a779a0-falcon-cpu.dtsi"
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#include "r8a779a0-falcon-csi-dsi.dtsi"
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#include "r8a779a0-falcon-ethernet.dtsi"
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2021-04-25 20:28:00 +00:00
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/ {
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model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
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compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
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aliases {
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ethernet0 = &avb0;
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};
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};
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&avb0 {
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pinctrl-0 = <&avb0_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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tx-internal-delay-ps = <2000>;
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status = "okay";
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2023-01-26 20:01:32 +00:00
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0022.1622",
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"ethernet-phy-ieee802.3-c22";
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio4>;
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interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
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};
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};
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2023-09-17 14:13:11 +00:00
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&can_clk {
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clock-frequency = <40000000>;
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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channel1 {
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status = "okay";
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};
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};
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&i2c0 {
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eeprom@51 {
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compatible = "rohm,br24g01", "atmel,24c01";
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label = "breakout-board";
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reg = <0x51>;
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pagesize = <8>;
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};
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};
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&pfc {
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avb0_pins: avb0 {
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mux {
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groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
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"avb0_txcrefclk";
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function = "avb0";
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};
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pins_mdio {
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groups = "avb0_mdio";
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drive-strength = <21>;
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};
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pins_mii {
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groups = "avb0_rgmii";
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drive-strength = <21>;
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};
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};
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2023-09-17 14:13:11 +00:00
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can_clk_pins: can-clk {
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groups = "can_clk";
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function = "can_clk";
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};
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canfd0_pins: canfd0 {
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groups = "canfd0_data";
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function = "canfd0";
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};
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canfd1_pins: canfd1 {
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groups = "canfd1_data";
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function = "canfd1";
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};
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};
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