2018-05-06 21:58:06 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2012-09-28 09:56:37 +00:00
|
|
|
/*
|
|
|
|
* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
|
2018-01-17 06:37:47 +00:00
|
|
|
* (C) Copyright 2013 - 2018 Xilinx, Inc.
|
2012-09-28 09:56:37 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2019-11-14 19:57:46 +00:00
|
|
|
#include <init.h>
|
2020-07-28 10:45:47 +00:00
|
|
|
#include <log.h>
|
2018-02-21 16:04:28 +00:00
|
|
|
#include <dm/uclass.h>
|
2019-08-01 15:46:51 +00:00
|
|
|
#include <env.h>
|
2021-02-23 15:07:45 +00:00
|
|
|
#include <env_internal.h>
|
2014-02-24 10:16:32 +00:00
|
|
|
#include <fdtdec.h>
|
2014-04-25 11:51:17 +00:00
|
|
|
#include <fpga.h>
|
2019-01-25 11:36:06 +00:00
|
|
|
#include <malloc.h>
|
2021-08-27 10:53:32 +00:00
|
|
|
#include <memalign.h>
|
2014-04-25 11:51:17 +00:00
|
|
|
#include <mmc.h>
|
2018-06-08 11:45:14 +00:00
|
|
|
#include <watchdog.h>
|
2018-02-21 16:04:28 +00:00
|
|
|
#include <wdt.h>
|
2013-04-22 13:43:02 +00:00
|
|
|
#include <zynqpl.h>
|
2020-10-31 03:38:53 +00:00
|
|
|
#include <asm/global_data.h>
|
2013-04-12 14:33:08 +00:00
|
|
|
#include <asm/arch/hardware.h>
|
|
|
|
#include <asm/arch/sys_proto.h>
|
2020-03-31 10:39:37 +00:00
|
|
|
#include "../common/board.h"
|
2012-09-28 09:56:37 +00:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2022-02-17 13:28:41 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
|
|
|
|
void board_debug_uart_init(void)
|
|
|
|
{
|
|
|
|
/* Add initialization sequence if UART is not configured */
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-09-28 09:56:37 +00:00
|
|
|
int board_init(void)
|
|
|
|
{
|
2021-02-02 15:34:48 +00:00
|
|
|
if (IS_ENABLED(CONFIG_SPL_BUILD))
|
|
|
|
printf("Silicon version:\t%d\n", zynq_get_silicon_version());
|
|
|
|
|
2012-09-28 09:56:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-08 20:18:21 +00:00
|
|
|
int board_late_init(void)
|
|
|
|
{
|
2019-01-25 11:36:06 +00:00
|
|
|
int env_targets_len = 0;
|
|
|
|
const char *mode;
|
|
|
|
char *new_targets;
|
|
|
|
char *env_targets;
|
|
|
|
|
2020-07-28 10:45:47 +00:00
|
|
|
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
|
|
|
|
debug("Saved variables - Skipping\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
|
|
|
|
return 0;
|
|
|
|
|
2014-01-08 20:18:21 +00:00
|
|
|
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
|
2016-12-16 12:16:14 +00:00
|
|
|
case ZYNQ_BM_QSPI:
|
2019-01-25 11:36:06 +00:00
|
|
|
mode = "qspi";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "qspiboot");
|
2016-12-16 12:16:14 +00:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_NAND:
|
2019-01-25 11:36:06 +00:00
|
|
|
mode = "nand";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "nandboot");
|
2016-12-16 12:16:14 +00:00
|
|
|
break;
|
2014-01-08 20:18:21 +00:00
|
|
|
case ZYNQ_BM_NOR:
|
2019-01-25 11:36:06 +00:00
|
|
|
mode = "nor";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "norboot");
|
2014-01-08 20:18:21 +00:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_SD:
|
2019-09-11 10:51:49 +00:00
|
|
|
mode = "mmc0";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "sdboot");
|
2014-01-08 20:18:21 +00:00
|
|
|
break;
|
|
|
|
case ZYNQ_BM_JTAG:
|
2019-11-14 04:13:44 +00:00
|
|
|
mode = "jtag pxe dhcp";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "jtagboot");
|
2014-01-08 20:18:21 +00:00
|
|
|
break;
|
|
|
|
default:
|
2019-01-25 11:36:06 +00:00
|
|
|
mode = "";
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("modeboot", "");
|
2014-01-08 20:18:21 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-01-25 11:36:06 +00:00
|
|
|
/*
|
|
|
|
* One terminating char + one byte for space between mode
|
|
|
|
* and default boot_targets
|
|
|
|
*/
|
|
|
|
env_targets = env_get("boot_targets");
|
|
|
|
if (env_targets)
|
|
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
|
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
|
|
|
|
if (!new_targets)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
sprintf(new_targets, "%s %s", mode,
|
|
|
|
env_targets ? env_targets : "");
|
|
|
|
|
|
|
|
env_set("boot_targets", new_targets);
|
|
|
|
|
2020-03-31 10:39:37 +00:00
|
|
|
return board_late_init_xilinx();
|
2014-01-08 20:18:21 +00:00
|
|
|
}
|
2012-09-28 09:56:37 +00:00
|
|
|
|
2016-04-01 13:56:33 +00:00
|
|
|
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
|
2017-03-31 14:40:32 +00:00
|
|
|
int dram_init_banksize(void)
|
2016-12-09 12:56:54 +00:00
|
|
|
{
|
2017-11-03 14:25:51 +00:00
|
|
|
return fdtdec_setup_memory_banksize();
|
2016-12-09 12:56:54 +00:00
|
|
|
}
|
2016-12-06 15:31:53 +00:00
|
|
|
|
2016-12-09 12:56:54 +00:00
|
|
|
int dram_init(void)
|
|
|
|
{
|
2018-07-16 10:26:11 +00:00
|
|
|
if (fdtdec_setup_mem_size_base() != 0)
|
2016-12-18 14:03:34 +00:00
|
|
|
return -EINVAL;
|
2016-12-04 09:33:22 +00:00
|
|
|
|
2016-12-09 12:56:54 +00:00
|
|
|
zynq_ddrc_init();
|
2016-12-04 09:33:22 +00:00
|
|
|
|
2016-12-09 12:56:54 +00:00
|
|
|
return 0;
|
2016-04-01 13:56:33 +00:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
int dram_init(void)
|
|
|
|
{
|
2018-04-11 14:12:28 +00:00
|
|
|
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
|
|
|
CONFIG_SYS_SDRAM_SIZE);
|
2016-04-01 13:56:33 +00:00
|
|
|
|
2013-06-17 12:37:01 +00:00
|
|
|
zynq_ddrc_init();
|
|
|
|
|
2012-09-28 09:56:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2016-04-01 13:56:33 +00:00
|
|
|
#endif
|
2021-02-23 15:07:45 +00:00
|
|
|
|
|
|
|
enum env_location env_get_location(enum env_operation op, int prio)
|
|
|
|
{
|
|
|
|
u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
|
|
|
|
|
|
|
|
if (prio)
|
|
|
|
return ENVL_UNKNOWN;
|
|
|
|
|
|
|
|
switch (bootmode) {
|
|
|
|
case ZYNQ_BM_SD:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
|
|
|
|
return ENVL_FAT;
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
|
|
|
|
return ENVL_EXT4;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2021-02-23 15:07:45 +00:00
|
|
|
case ZYNQ_BM_NAND:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
|
|
|
|
return ENVL_NAND;
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
|
|
|
|
return ENVL_UBI;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2021-02-23 15:07:45 +00:00
|
|
|
case ZYNQ_BM_NOR:
|
|
|
|
case ZYNQ_BM_QSPI:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
|
|
|
|
return ENVL_SPI_FLASH;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2021-02-23 15:07:45 +00:00
|
|
|
case ZYNQ_BM_JTAG:
|
|
|
|
default:
|
|
|
|
return ENVL_NOWHERE;
|
|
|
|
}
|
|
|
|
}
|
2021-08-27 10:53:32 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_SET_DFU_ALT_INFO)
|
|
|
|
|
|
|
|
#define DFU_ALT_BUF_LEN SZ_1K
|
|
|
|
|
|
|
|
void set_dfu_alt_info(char *interface, char *devstr)
|
|
|
|
{
|
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
|
|
|
|
|
|
|
|
if (env_get("dfu_alt_info"))
|
|
|
|
return;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
|
|
|
|
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
|
|
|
|
case ZYNQ_BM_SD:
|
|
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
|
|
"mmc 0:1=boot.bin fat 0 1;"
|
|
|
|
"u-boot.img fat 0 1");
|
|
|
|
break;
|
|
|
|
case ZYNQ_BM_QSPI:
|
|
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
|
|
"sf 0:0=boot.bin raw 0 0x1500000;"
|
|
|
|
"u-boot.img raw 0x%x 0x500000",
|
|
|
|
CONFIG_SYS_SPI_U_BOOT_OFFS);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
env_set("dfu_alt_info", buf);
|
|
|
|
puts("DFU alt info setting: done\n");
|
|
|
|
}
|
|
|
|
#endif
|