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u-boot/board/xilinx/zynq
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Michal Simek 05f0f269b7 ARM: zynq: Fix debug uart initialization 
The commit 0dba45864b ("arm: Init the debug UART") calls
debug_uart_init() from crt0.S but it won't work because SOC is not
configured yet. That's why create board_debug_uart_init() which calls
ps7_init() earlier before the first access to UART.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/18e67e02a0c7190839a1ef3a11f3fd6babcf34cc.1645104518.git.michal.simek@xilinx.com
2022-02-21 13:20:24 +01:00
..
zynq-cc108 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-dlc20-rev1.0 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-microzed WS cleanup: remove excessive empty lines 2021-09-30 08:08:56 -04:00
zynq-zc702 WS cleanup: remove excessive empty lines 2021-09-30 08:08:56 -04:00
zynq-zc706 WS cleanup: remove excessive empty lines 2021-09-30 08:08:56 -04:00
zynq-zc770-xm010 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zc770-xm011 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zc770-xm011-x16 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zc770-xm012 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zc770-xm013 arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zed WS cleanup: remove excessive empty lines 2021-09-30 08:08:56 -04:00
zynq-zturn arm: zynq: Remove low level UART setting 2020-01-14 09:05:53 +01:00
zynq-zturn-v5 ARM: zynq: Add Z-turn board V5 2020-10-27 08:01:36 +01:00
zynq-zybo WS cleanup: remove trailing empty lines 2021-09-30 08:08:56 -04:00
zynq-zybo-z7 arm: zynq: zybo z7: fix MIO init issue 2020-02-28 12:04:10 +01:00
.gitignore ARM: zynq: add default ps7_init_gpl.c/h for Zed, MicroZed, ZC70x 2015-05-25 10:52:36 +02:00
board.c ARM: zynq: Fix debug uart initialization 2022-02-21 13:20:24 +01:00
bootimg.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
cmds.c global: Convert simple_strtoul() with hex to hextoul() 2021-08-02 13:32:14 -04:00
Kconfig xilinx: zynq: Add support to secure images 2018-07-19 10:49:54 +02:00
MAINTAINERS Correct U-Boot upstream repository 2021-02-28 13:57:30 -05:00
Makefile xilinx: common: Add Makefile to common folder 2020-10-27 08:13:32 +01:00
xil_io.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
zynq-cse-nand ARM: zynq: Wire SPL configuration for cse nor/nand targets 2018-11-29 10:31:02 +01:00
zynq-cse-nor ARM: zynq: Wire SPL configuration for cse nor/nand targets 2018-11-29 10:31:02 +01:00
zynq-cse-qspi-single arm: zynq: Add mini u-boot configuration for zynq 2017-11-28 16:08:47 +01:00