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u-boot/arch/x86/cpu/start_from_spl.S

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x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
/*
x86: Add more comments to the start-up code The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since each phase has its own 'start' file. Add comments to explain this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 14:11:44 +00:00
* 32-bit x86 Startup Code when running from SPL. This is the startup code in
* U-Boot proper, when SPL is used.
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
* Copyright 2018 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <config.h>
.section .text.start
.code32
.globl _start
.type _start, @function
_start:
x86: Use the existing stack when chain-loading With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:13:00 +00:00
/*
* If running from coreboot, CAR is no-longer available. Use the
* existing stack, which is large enough.
*/
call locate_coreboot_table
cmp $0, %eax
jge use_existing_stack
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %eax
#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %eax
#endif
x86: Use the existing stack when chain-loading With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:13:00 +00:00
jmp 2f
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
/*
x86: Use the existing stack when chain-loading With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:13:00 +00:00
* We don't subtract CONFIG_DCACHE_RAM_MRC_VAR_SIZE since memory is
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
* already set up. This has the happy side-effect of putting gd in a
* new place separate from SPL, so the memset() in
* board_init_f_init_reserve() does not cause any problems (otherwise
* it would zero out the gd and crash)
*/
x86: Use the existing stack when chain-loading With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-26 15:13:00 +00:00
/* Set up memory using the existing stack */
use_existing_stack:
mov %esp, %eax
2:
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
call board_init_f_alloc_reserve
mov %eax, %esp
call board_init_f_init_reserve
x86: Move CPU init to before spl_init() At present we call spl_init() before identifying the CPU. This is not a good idea - e.g. if bootstage is enabled then it will try to set up the timer which works better if the CPU is identified. Put explicit code at each entry pointer to identify the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-21 03:37:55 +00:00
call x86_cpu_reinit_f
x86: Add support for starting from SPL/TPL When a previous phase of U-Boot has run we need to adjust the init of subsequent states to avoid messing up the CPU state. Add a new version of the start logic for SPL, when it boots from TPL (start_from tpl.c) and a new version for U-Boot when it boots from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:52 +00:00
xorl %eax, %eax
call board_init_f
call board_init_f_r
/* Should not return here */
jmp .
.globl board_init_f_r_trampoline
.type board_init_f_r_trampoline, @function
board_init_f_r_trampoline:
/*
* SPL has been executed and SDRAM has been initialised, U-Boot code
* has been copied into RAM, BSS has been cleared and relocation
* adjustments have been made. It is now time to jump into the in-RAM
* copy of U-Boot
*
* %eax = Address of top of new stack
*/
/* Stack grows down from top of SDRAM */
movl %eax, %esp
/* Re-enter U-Boot by calling board_init_f_r() */
call board_init_f_r
die:
hlt
jmp die
hlt
.align 4
_dt_ucode_base_size:
/* These next two fields are filled in by binman */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
.globl ucode_size
ucode_size: /* Declared in microcode.h */
.long 0 /* microcode size */
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