u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
 */

#ifndef _RESET_MANAGER_GEN5_H_
#define _RESET_MANAGER_GEN5_H_

#include <dt-bindings/reset/altr,rst-mgr.h>

void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);

#define RSTMGR_GEN5_STATUS	0x00
#define RSTMGR_GEN5_CTRL	0x04
#define RSTMGR_GEN5_MPUMODRST	0x10
#define RSTMGR_GEN5_PERMODRST	0x14
#define RSTMGR_GEN5_PER2MODRST	0x18
#define RSTMGR_GEN5_BRGMODRST	0x1c
#define RSTMGR_GEN5_MISCMODRST	0x20

#define RSTMGR_CTRL		RSTMGR_GEN5_CTRL

/*
 * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
 * 0 ... mpumodrst
 * 1 ... permodrst
 * 2 ... per2modrst
 * 3 ... brgmodrst
 * 4 ... miscmodrst
 */
#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)

#endif /* _RESET_MANAGER_GEN5_H_ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:34 +00:00			`/*`
			`* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>`
			`*/`

			`#ifndef _RESET_MANAGER_GEN5_H_`
			`#define _RESET_MANAGER_GEN5_H_`

			`#include <dt-bindings/reset/altr,rst-mgr.h>`

ARM: socfpga: Factor out handoff register configuration Factor out the code for programming preloader handoff register values, the ISWGRP Handoff 0 and 1. These registers later control which bridges are enabled by the "bridge" command on Gen5 devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> 2019-04-16 21:05:24 +00:00			`void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);`
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:34 +00:00			`void socfpga_bridges_reset(int enable);`

arm: socfpga: Convert reset manager from struct to defines Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 2019-11-08 02:38:19 +00:00			`#define RSTMGR_GEN5_STATUS 0x00`
			`#define RSTMGR_GEN5_CTRL 0x04`
			`#define RSTMGR_GEN5_MPUMODRST 0x10`
			`#define RSTMGR_GEN5_PERMODRST 0x14`
			`#define RSTMGR_GEN5_PER2MODRST 0x18`
			`#define RSTMGR_GEN5_BRGMODRST 0x1c`
			`#define RSTMGR_GEN5_MISCMODRST 0x20`

			`#define RSTMGR_CTRL RSTMGR_GEN5_CTRL`
arm: socfpga: Restructure reset manager driver Restructure reset manager driver in the preparation to support A10. Move the Gen5 specific code to gen5 files. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-25 18:44:34 +00:00
			`/*`
			`* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:`
			`* 0 ... mpumodrst`
			`* 1 ... permodrst`
			`* 2 ... per2modrst`
			`* 3 ... brgmodrst`
			`* 4 ... miscmodrst`
			`*/`
			`#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)`
			`#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)`
			`#define RSTMGR_NAND RSTMGR_DEFINE(1, 4)`
			`#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)`
			`#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)`
			`#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)`
			`#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)`
			`#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)`
			`#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)`
			`#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)`
			`#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)`
			`#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)`

			`#endif /* _RESET_MANAGER_GEN5_H_ */`