2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2016-10-08 12:30:11 +00:00
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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2016-10-08 12:30:13 +00:00
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#include <asm/arch/crm_regs.h>
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2016-10-08 12:30:11 +00:00
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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2017-06-29 08:16:06 +00:00
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/video.h>
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2016-10-08 12:30:11 +00:00
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2017-05-06 21:13:14 +00:00
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#include "../common/board.h"
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2016-10-25 06:23:23 +00:00
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#ifdef CONFIG_NAND_MXS
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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2017-11-20 18:32:16 +00:00
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static iomux_v3_cfg_t gpmi_pads[] = {
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2016-10-25 06:23:23 +00:00
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IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
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IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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};
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2017-05-06 21:13:14 +00:00
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void setup_gpmi_nand(void)
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2016-10-25 06:23:23 +00:00
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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SETUP_IOMUX_PADS(gpmi_pads);
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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2016-12-05 23:00:55 +00:00
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#if defined(CONFIG_VIDEO_IPUV3)
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static iomux_v3_cfg_t const rgb_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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};
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static void enable_rgb(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(rgb_pads);
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}
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struct display_info_t const displays[] = {
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{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.detect = NULL,
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.enable = enable_rgb,
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.mode = {
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.name = "Amp-WD",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30000,
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.left_margin = 30,
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.right_margin = 30,
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.upper_margin = 5,
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.lower_margin = 5,
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.hsync_len = 64,
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.vsync_len = 20,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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}
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},
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};
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size_t display_count = ARRAY_SIZE(displays);
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2017-05-06 21:13:14 +00:00
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void setup_display(void)
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2016-12-05 23:00:55 +00:00
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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/* Turn on LDB0,IPU,IPU DI0 clocks */
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reg = __raw_readl(&mxc_ccm->CCGR3);
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reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
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writel(reg, &mxc_ccm->CCGR3);
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/* set LDB0, LDB1 clk select to 011/011 */
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reg = readl(&mxc_ccm->cs2cdr);
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reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
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MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
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reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
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(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->cs2cdr);
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reg = readl(&mxc_ccm->cscmr2);
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reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
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writel(reg, &mxc_ccm->cscmr2);
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
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IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
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IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
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IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
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IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
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IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
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IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
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IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
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writel(reg, &iomux->gpr[2]);
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reg = readl(&iomux->gpr[3]);
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reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
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(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
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IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
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writel(reg, &iomux->gpr[3]);
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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2017-11-20 18:32:16 +00:00
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#ifdef CONFIG_ENV_IS_IN_MMC
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int board_mmc_get_env_dev(int devno)
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{
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2017-11-20 18:32:17 +00:00
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/* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
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return (devno == 0) ? 0: (devno - 1);
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2017-11-20 18:32:16 +00:00
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}
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#endif
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