2010-06-08 20:07:46 +00:00
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Authors:
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* Aneesh V <aneesh@ti.com>
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*
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* Derived from OMAP3 work by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP4_H_
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#define _OMAP4_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP44XX_L4_CORE_BASE 0x4A000000
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#define OMAP44XX_L4_WKUP_BASE 0x4A300000
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#define OMAP44XX_L4_PER_BASE 0x48000000
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2010-09-12 05:02:55 +00:00
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#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
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#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
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2011-11-15 14:49:55 +00:00
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#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
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#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
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2010-09-12 05:02:55 +00:00
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2010-06-08 20:07:46 +00:00
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/* CONTROL */
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#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
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2010-07-15 20:43:10 +00:00
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#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
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#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
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2010-06-08 20:07:46 +00:00
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2011-07-21 13:10:09 +00:00
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/* LPDDR2 IO regs */
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#define LPDDR2_IO_REGS_BASE 0x4A100638
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2011-07-21 13:10:04 +00:00
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/* CONTROL_ID_CODE */
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#define CONTROL_ID_CODE 0x4A002204
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2011-11-15 14:49:55 +00:00
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#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
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#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
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#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
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#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
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#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
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2011-11-21 23:39:03 +00:00
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#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
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#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
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2011-09-21 10:17:30 +00:00
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2010-06-08 20:07:46 +00:00
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/* UART */
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#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
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#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
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#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
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/* General Purpose Timers */
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#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
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#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
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#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
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/* Watchdog Timer2 - MPU watchdog */
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#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
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/* 32KTIMER */
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#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
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/* GPMC */
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2010-07-15 20:19:16 +00:00
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#define OMAP44XX_GPMC_BASE 0x50000000
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2010-06-08 20:07:46 +00:00
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2011-09-08 15:05:56 +00:00
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/* SYSTEM CONTROL MODULE */
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#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
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2010-06-08 20:07:46 +00:00
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/*
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* Hardware Register Details
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*/
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/* Watchdog Timer */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* GP Timer */
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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2011-09-08 15:05:56 +00:00
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/* Control Module */
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#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
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#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
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#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
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2011-12-29 08:47:17 +00:00
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#define CONTROL_EFUSE_2_OVERRIDE 0x99084000
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2011-09-08 15:05:56 +00:00
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
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#define LPDDR2IO_GR10_WD_MASK (3 << 17)
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2012-05-24 00:30:25 +00:00
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#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
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2011-09-08 15:05:56 +00:00
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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2011-09-08 06:34:57 +00:00
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#define MMC1_PWRDNZ (1 << 26)
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#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
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#define MMC1_PBIASLITE_VMODE (1 << 21)
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2010-06-08 20:07:46 +00:00
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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};
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2012-03-12 02:25:43 +00:00
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#define DEVICE_TYPE_SHIFT (0x8)
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#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
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#define DEVICE_GP 0x3
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2012-03-12 02:25:42 +00:00
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struct omap_sys_ctrl_regs {
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2011-09-08 15:05:56 +00:00
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unsigned int pad1[129];
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unsigned int control_id_code; /* 0x4A002204 */
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unsigned int pad11[22];
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unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
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2012-03-12 02:25:42 +00:00
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unsigned int pad2[24]; /* 0x4a002264 */
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unsigned int control_status; /* 0x4a0022c4 */
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unsigned int pad3[22]; /* 0x4a0022c8 */
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2011-09-08 15:05:56 +00:00
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unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
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unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
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unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
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2012-03-12 02:25:42 +00:00
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unsigned int pad4[260277];
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2011-11-15 14:49:55 +00:00
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unsigned int control_pbiaslite; /* 0x4A100600 */
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2012-03-12 02:25:42 +00:00
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unsigned int pad5[63];
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2011-09-08 15:05:56 +00:00
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unsigned int control_efuse_1; /* 0x4A100700 */
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unsigned int control_efuse_2; /* 0x4A100704 */
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};
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struct control_lpddr2io_regs {
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unsigned int control_lpddr2io1_0;
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unsigned int control_lpddr2io1_1;
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unsigned int control_lpddr2io1_2;
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unsigned int control_lpddr2io1_3;
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unsigned int control_lpddr2io2_0;
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unsigned int control_lpddr2io2_1;
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unsigned int control_lpddr2io2_2;
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unsigned int control_lpddr2io2_3;
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};
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2010-06-08 20:07:46 +00:00
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#endif /* __ASSEMBLY__ */
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/*
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* Non-secure SRAM Addresses
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* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
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* at 0x40304000(EMU base) so that our code works for both EMU and GP
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*/
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#define NON_SECURE_SRAM_START 0x40304000
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#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_ROM_VECT_BASE 0x4030D000
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/* Temporary SRAM stack used while low level init is done */
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2011-07-21 13:10:04 +00:00
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#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
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/* SRAM scratch space entries */
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#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
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2011-07-21 13:10:12 +00:00
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#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
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#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
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#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
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#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
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2011-07-21 13:10:04 +00:00
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2011-07-21 13:10:27 +00:00
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/* ROM code defines */
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/* Boot device */
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#define BOOT_DEVICE_MASK 0xFF
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#define BOOT_DEVICE_OFFSET 0x8
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#define DEV_DESC_PTR_OFFSET 0x4
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#define DEV_DATA_PTR_OFFSET 0x18
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#define BOOT_MODE_OFFSET 0x8
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2011-11-15 14:50:03 +00:00
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#define RESET_REASON_OFFSET 0x9
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#define CH_FLAGS_OFFSET 0xA
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2011-07-21 13:10:27 +00:00
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2011-11-15 14:50:03 +00:00
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#define CH_FLAGS_CHSETTINGS (0x1 << 0)
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#define CH_FLAGS_CHRAM (0x1 << 1)
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#define CH_FLAGS_CHFLASH (0x1 << 2)
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#define CH_FLAGS_CHMMCSD (0x1 << 3)
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#ifndef __ASSEMBLY__
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struct omap_boot_parameters {
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char *boot_message;
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unsigned int mem_boot_descriptor;
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unsigned char omap_bootdevice;
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unsigned char reset_reason;
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unsigned char ch_flags;
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};
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#endif
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2010-06-08 20:07:46 +00:00
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#endif
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