2019-11-06 15:16:32 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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2017-09-13 16:00:09 +00:00
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/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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*/
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#include "armv7-m.dtsi"
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ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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#include <dt-bindings/clock/stm32h7-clks.h>
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2017-10-03 13:54:56 +00:00
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#include <dt-bindings/mfd/stm32h7-rcc.h>
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2018-12-06 10:53:39 +00:00
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#include <dt-bindings/interrupt-controller/irq.h>
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2017-09-13 16:00:09 +00:00
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/ {
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2019-11-06 15:16:32 +00:00
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#address-cells = <1>;
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#size-cells = <1>;
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2017-09-13 16:00:09 +00:00
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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2018-12-06 10:53:39 +00:00
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clock-frequency = <0>;
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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2017-09-13 16:00:09 +00:00
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};
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|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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clk_i2s: i2s_ckin {
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2017-09-13 16:00:09 +00:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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clock-frequency = <0>;
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2017-09-13 16:00:09 +00:00
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};
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};
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soc {
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2018-12-06 10:53:39 +00:00
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc TIM5_CK>;
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ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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};
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2018-12-06 10:53:39 +00:00
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lptimer1: timer@40002400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x40002400 0x400>;
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clocks = <&rcc LPTIM1_CK>;
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clock-names = "mux";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@0 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-lptimer-counter";
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status = "disabled";
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};
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};
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spi2: spi@40003800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40003800 0x400>;
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interrupts = <36>;
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2020-11-06 07:11:58 +00:00
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resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
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2018-12-06 10:53:39 +00:00
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clocks = <&rcc SPI2_CK>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32h7-spi";
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reg = <0x40003c00 0x400>;
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interrupts = <51>;
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2020-11-06 07:11:58 +00:00
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resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
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2018-12-06 10:53:39 +00:00
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clocks = <&rcc SPI3_CK>;
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2017-09-13 16:00:09 +00:00
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status = "disabled";
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};
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usart2: serial@40004400 {
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2020-11-06 07:11:58 +00:00
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compatible = "st,stm32h7-uart";
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2017-09-13 16:00:09 +00:00
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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status = "disabled";
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
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clocks = <&rcc USART2_CK>;
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2017-09-13 16:00:09 +00:00
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};
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2021-04-09 07:28:42 +00:00
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usart3: serial@40004800 {
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compatible = "st,stm32h7-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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status = "disabled";
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clocks = <&rcc USART3_CK>;
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32h7-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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status = "disabled";
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clocks = <&rcc UART4_CK>;
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};
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2018-12-06 10:53:39 +00:00
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i2c1: i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
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clocks = <&rcc I2C1_CK>;
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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interrupts = <33>,
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<34>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
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clocks = <&rcc I2C2_CK>;
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status = "disabled";
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};
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2021-04-09 07:28:43 +00:00
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i2c3: i2c@40005c00 {
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2018-12-06 10:53:39 +00:00
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compatible = "st,stm32f7-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005C00 0x400>;
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interrupts = <72>,
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<73>;
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resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
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clocks = <&rcc I2C3_CK>;
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status = "disabled";
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};
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dac: dac@40007400 {
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compatible = "st,stm32h7-dac-core";
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reg = <0x40007400 0x400>;
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clocks = <&rcc DAC12_CK>;
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clock-names = "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
dac1: dac@1 {
|
|
|
|
|
compatible = "st,stm32-dac";
|
2020-11-06 07:11:58 +00:00
|
|
|
#io-channel-cells = <1>;
|
2018-12-06 10:53:39 +00:00
|
|
|
reg = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dac2: dac@2 {
|
|
|
|
|
compatible = "st,stm32-dac";
|
2020-11-06 07:11:58 +00:00
|
|
|
#io-channel-cells = <1>;
|
2018-12-06 10:53:39 +00:00
|
|
|
reg = <2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usart1: serial@40011000 {
|
2020-11-06 07:11:58 +00:00
|
|
|
compatible = "st,stm32h7-uart";
|
2018-12-06 10:53:39 +00:00
|
|
|
reg = <0x40011000 0x400>;
|
|
|
|
|
interrupts = <37>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&rcc USART1_CK>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1: spi@40013000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32h7-spi";
|
|
|
|
|
reg = <0x40013000 0x400>;
|
|
|
|
|
interrupts = <35>;
|
2020-11-06 07:11:58 +00:00
|
|
|
resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
|
2018-12-06 10:53:39 +00:00
|
|
|
clocks = <&rcc SPI1_CK>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi4: spi@40013400 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32h7-spi";
|
|
|
|
|
reg = <0x40013400 0x400>;
|
|
|
|
|
interrupts = <84>;
|
2020-11-06 07:11:58 +00:00
|
|
|
resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
|
2018-12-06 10:53:39 +00:00
|
|
|
clocks = <&rcc SPI4_CK>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi5: spi@40015000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32h7-spi";
|
|
|
|
|
reg = <0x40015000 0x400>;
|
|
|
|
|
interrupts = <85>;
|
2020-11-06 07:11:58 +00:00
|
|
|
resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
|
2018-12-06 10:53:39 +00:00
|
|
|
clocks = <&rcc SPI5_CK>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-06 07:11:58 +00:00
|
|
|
dma1: dma-controller@40020000 {
|
2018-12-06 10:53:39 +00:00
|
|
|
compatible = "st,stm32-dma";
|
|
|
|
|
reg = <0x40020000 0x400>;
|
|
|
|
|
interrupts = <11>,
|
|
|
|
|
<12>,
|
|
|
|
|
<13>,
|
|
|
|
|
<14>,
|
|
|
|
|
<15>,
|
|
|
|
|
<16>,
|
|
|
|
|
<17>,
|
|
|
|
|
<47>;
|
|
|
|
|
clocks = <&rcc DMA1_CK>;
|
|
|
|
|
#dma-cells = <4>;
|
|
|
|
|
st,mem2mem;
|
|
|
|
|
dma-requests = <8>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-06 07:11:58 +00:00
|
|
|
dma2: dma-controller@40020400 {
|
2018-12-06 10:53:39 +00:00
|
|
|
compatible = "st,stm32-dma";
|
|
|
|
|
reg = <0x40020400 0x400>;
|
|
|
|
|
interrupts = <56>,
|
|
|
|
|
<57>,
|
|
|
|
|
<58>,
|
|
|
|
|
<59>,
|
|
|
|
|
<60>,
|
|
|
|
|
<68>,
|
|
|
|
|
<69>,
|
|
|
|
|
<70>;
|
|
|
|
|
clocks = <&rcc DMA2_CK>;
|
|
|
|
|
#dma-cells = <4>;
|
|
|
|
|
st,mem2mem;
|
|
|
|
|
dma-requests = <8>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dmamux1: dma-router@40020800 {
|
|
|
|
|
compatible = "st,stm32h7-dmamux";
|
2021-04-09 07:28:43 +00:00
|
|
|
reg = <0x40020800 0x40>;
|
2018-12-06 10:53:39 +00:00
|
|
|
#dma-cells = <3>;
|
|
|
|
|
dma-channels = <16>;
|
|
|
|
|
dma-requests = <128>;
|
|
|
|
|
dma-masters = <&dma1 &dma2>;
|
|
|
|
|
clocks = <&rcc DMA1_CK>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
adc_12: adc@40022000 {
|
|
|
|
|
compatible = "st,stm32h7-adc-core";
|
|
|
|
|
reg = <0x40022000 0x400>;
|
|
|
|
|
interrupts = <18>;
|
|
|
|
|
clocks = <&rcc ADC12_CK>;
|
|
|
|
|
clock-names = "bus";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
adc1: adc@0 {
|
|
|
|
|
compatible = "st,stm32h7-adc";
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
interrupt-parent = <&adc_12>;
|
|
|
|
|
interrupts = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
adc2: adc@100 {
|
|
|
|
|
compatible = "st,stm32h7-adc";
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
reg = <0x100>;
|
|
|
|
|
interrupt-parent = <&adc_12>;
|
|
|
|
|
interrupts = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbotg_hs: usb@40040000 {
|
|
|
|
|
compatible = "st,stm32f7-hsotg";
|
|
|
|
|
reg = <0x40040000 0x40000>;
|
|
|
|
|
interrupts = <77>;
|
|
|
|
|
clocks = <&rcc USB1OTG_CK>;
|
|
|
|
|
clock-names = "otg";
|
|
|
|
|
g-rx-fifo-size = <256>;
|
|
|
|
|
g-np-tx-fifo-size = <32>;
|
|
|
|
|
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbotg_fs: usb@40080000 {
|
|
|
|
|
compatible = "st,stm32f4x9-fsotg";
|
|
|
|
|
reg = <0x40080000 0x40000>;
|
|
|
|
|
interrupts = <101>;
|
|
|
|
|
clocks = <&rcc USB2OTG_CK>;
|
|
|
|
|
clock-names = "otg";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-06 07:11:58 +00:00
|
|
|
ltdc: display-controller@50001000 {
|
|
|
|
|
compatible = "st,stm32-ltdc";
|
|
|
|
|
reg = <0x50001000 0x200>;
|
|
|
|
|
interrupts = <88>, <89>;
|
|
|
|
|
resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
|
|
|
|
|
clocks = <&rcc LTDC_CK>;
|
|
|
|
|
clock-names = "lcd";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mdma1: dma-controller@52000000 {
|
2018-12-06 10:53:39 +00:00
|
|
|
compatible = "st,stm32h7-mdma";
|
|
|
|
|
reg = <0x52000000 0x1000>;
|
|
|
|
|
interrupts = <122>;
|
|
|
|
|
clocks = <&rcc MDMA_CK>;
|
|
|
|
|
#dma-cells = <5>;
|
|
|
|
|
dma-channels = <16>;
|
|
|
|
|
dma-requests = <32>;
|
|
|
|
|
};
|
|
|
|
|
|
2022-09-23 11:20:33 +00:00
|
|
|
sdmmc1: mmc@52007000 {
|
2019-11-06 15:16:32 +00:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
arm,primecell-periphid = <0x10153180>;
|
|
|
|
|
reg = <0x52007000 0x1000>;
|
|
|
|
|
interrupts = <49>;
|
|
|
|
|
clocks = <&rcc SDMMC1_CK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
|
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
|
max-frequency = <120000000>;
|
|
|
|
|
};
|
|
|
|
|
|
2022-09-23 11:20:33 +00:00
|
|
|
sdmmc2: mmc@48022400 {
|
2021-04-09 07:28:42 +00:00
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
arm,primecell-periphid = <0x10153180>;
|
|
|
|
|
reg = <0x48022400 0x400>;
|
|
|
|
|
interrupts = <124>;
|
|
|
|
|
clocks = <&rcc SDMMC2_CK>;
|
|
|
|
|
clock-names = "apb_pclk";
|
|
|
|
|
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
|
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
|
max-frequency = <120000000>;
|
2022-09-23 11:20:33 +00:00
|
|
|
status = "disabled";
|
2021-04-09 07:28:42 +00:00
|
|
|
};
|
|
|
|
|
|
2018-12-06 10:53:39 +00:00
|
|
|
exti: interrupt-controller@58000000 {
|
|
|
|
|
compatible = "st,stm32h7-exti";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
reg = <0x58000000 0x400>;
|
|
|
|
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-06 07:11:58 +00:00
|
|
|
syscfg: syscon@58000400 {
|
|
|
|
|
compatible = "st,stm32-syscfg", "syscon";
|
2018-12-06 10:53:39 +00:00
|
|
|
reg = <0x58000400 0x400>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi6: spi@58001400 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32h7-spi";
|
|
|
|
|
reg = <0x58001400 0x400>;
|
|
|
|
|
interrupts = <86>;
|
2020-11-06 07:11:58 +00:00
|
|
|
resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
|
2018-12-06 10:53:39 +00:00
|
|
|
clocks = <&rcc SPI6_CK>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2021-04-09 07:28:43 +00:00
|
|
|
i2c4: i2c@58001c00 {
|
2018-12-06 10:53:39 +00:00
|
|
|
compatible = "st,stm32f7-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x58001C00 0x400>;
|
|
|
|
|
interrupts = <95>,
|
|
|
|
|
<96>;
|
|
|
|
|
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
|
|
|
|
|
clocks = <&rcc I2C4_CK>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lptimer2: timer@58002400 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32-lptimer";
|
|
|
|
|
reg = <0x58002400 0x400>;
|
|
|
|
|
clocks = <&rcc LPTIM2_CK>;
|
|
|
|
|
clock-names = "mux";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm-lp";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
trigger@1 {
|
|
|
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
counter {
|
|
|
|
|
compatible = "st,stm32-lptimer-counter";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lptimer3: timer@58002800 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "st,stm32-lptimer";
|
|
|
|
|
reg = <0x58002800 0x400>;
|
|
|
|
|
clocks = <&rcc LPTIM3_CK>;
|
|
|
|
|
clock-names = "mux";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm-lp";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
trigger@2 {
|
|
|
|
|
compatible = "st,stm32-lptimer-trigger";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lptimer4: timer@58002c00 {
|
|
|
|
|
compatible = "st,stm32-lptimer";
|
|
|
|
|
reg = <0x58002c00 0x400>;
|
|
|
|
|
clocks = <&rcc LPTIM4_CK>;
|
|
|
|
|
clock-names = "mux";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm-lp";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
lptimer5: timer@58003000 {
|
|
|
|
|
compatible = "st,stm32-lptimer";
|
|
|
|
|
reg = <0x58003000 0x400>;
|
|
|
|
|
clocks = <&rcc LPTIM5_CK>;
|
|
|
|
|
clock-names = "mux";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm-lp";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vrefbuf: regulator@58003c00 {
|
|
|
|
|
compatible = "st,stm32-vrefbuf";
|
|
|
|
|
reg = <0x58003C00 0x8>;
|
|
|
|
|
clocks = <&rcc VREF_CK>;
|
|
|
|
|
regulator-min-microvolt = <1500000>;
|
|
|
|
|
regulator-max-microvolt = <2500000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rtc: rtc@58004000 {
|
|
|
|
|
compatible = "st,stm32h7-rtc";
|
|
|
|
|
reg = <0x58004000 0x400>;
|
|
|
|
|
clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
|
|
|
|
|
clock-names = "pclk", "rtc_ck";
|
|
|
|
|
assigned-clocks = <&rcc RTC_CK>;
|
|
|
|
|
assigned-clock-parents = <&rcc LSE_CK>;
|
|
|
|
|
interrupt-parent = <&exti>;
|
|
|
|
|
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
st,syscfg = <&pwrcfg 0x00 0x100>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rcc: reset-clock-controller@58024400 {
|
|
|
|
|
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
|
|
|
|
reg = <0x58024400 0x400>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
|
|
|
|
|
st,syscfg = <&pwrcfg>;
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwrcfg: power-config@58024800 {
|
2020-11-06 07:11:58 +00:00
|
|
|
compatible = "st,stm32-power-config", "syscon";
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
|
|
|
reg = <0x58024800 0x400>;
|
|
|
|
|
};
|
|
|
|
|
|
2018-12-06 10:53:39 +00:00
|
|
|
adc_3: adc@58026000 {
|
|
|
|
|
compatible = "st,stm32h7-adc-core";
|
|
|
|
|
reg = <0x58026000 0x400>;
|
|
|
|
|
interrupts = <127>;
|
|
|
|
|
clocks = <&rcc ADC3_CK>;
|
|
|
|
|
clock-names = "bus";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
ARM: DTS: stm32: adapt stm32h7 dts files for U-boot
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:11 +00:00
|
|
|
|
2018-12-06 10:53:39 +00:00
|
|
|
adc3: adc@0 {
|
|
|
|
|
compatible = "st,stm32h7-adc";
|
|
|
|
|
#io-channel-cells = <1>;
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
interrupt-parent = <&adc_3>;
|
|
|
|
|
interrupts = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2017-09-13 16:00:09 +00:00
|
|
|
};
|
2019-11-06 15:16:32 +00:00
|
|
|
|
|
|
|
|
mac: ethernet@40028000 {
|
|
|
|
|
compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
|
|
|
|
|
reg = <0x40028000 0x8000>;
|
|
|
|
|
reg-names = "stmmaceth";
|
|
|
|
|
interrupts = <61>;
|
|
|
|
|
interrupt-names = "macirq";
|
|
|
|
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
|
|
|
|
clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
|
|
|
|
|
st,syscon = <&syscfg 0x4>;
|
|
|
|
|
snps,pbl = <8>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2021-04-09 07:28:41 +00:00
|
|
|
|
2022-09-23 11:20:33 +00:00
|
|
|
pinctrl: pinctrl@58020000 {
|
2021-04-09 07:28:41 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stm32h743-pinctrl";
|
|
|
|
|
ranges = <0 0x58020000 0x3000>;
|
|
|
|
|
interrupt-parent = <&exti>;
|
|
|
|
|
st,syscfg = <&syscfg 0x8>;
|
|
|
|
|
pins-are-numbered;
|
|
|
|
|
|
|
|
|
|
gpioa: gpio@58020000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x0 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOA_CK>;
|
|
|
|
|
st,bank-name = "GPIOA";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 0 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpiob: gpio@58020400 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x400 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOB_CK>;
|
|
|
|
|
st,bank-name = "GPIOB";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 16 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpioc: gpio@58020800 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x800 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOC_CK>;
|
|
|
|
|
st,bank-name = "GPIOC";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 32 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpiod: gpio@58020c00 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0xc00 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOD_CK>;
|
|
|
|
|
st,bank-name = "GPIOD";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 48 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpioe: gpio@58021000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x1000 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOE_CK>;
|
|
|
|
|
st,bank-name = "GPIOE";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 64 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpiof: gpio@58021400 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x1400 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOF_CK>;
|
|
|
|
|
st,bank-name = "GPIOF";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 80 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpiog: gpio@58021800 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x1800 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOG_CK>;
|
|
|
|
|
st,bank-name = "GPIOG";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 96 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpioh: gpio@58021c00 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x1c00 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOH_CK>;
|
|
|
|
|
st,bank-name = "GPIOH";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 112 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpioi: gpio@58022000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x2000 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOI_CK>;
|
|
|
|
|
st,bank-name = "GPIOI";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 128 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpioj: gpio@58022400 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x2400 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOJ_CK>;
|
|
|
|
|
st,bank-name = "GPIOJ";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <16>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 144 16>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpiok: gpio@58022800 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
reg = <0x2800 0x400>;
|
|
|
|
|
clocks = <&rcc GPIOK_CK>;
|
|
|
|
|
st,bank-name = "GPIOK";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ngpios = <8>;
|
|
|
|
|
gpio-ranges = <&pinctrl 0 160 8>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2017-09-13 16:00:09 +00:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&systick {
|
|
|
|
|
clock-frequency = <250000000>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
