2015-06-23 21:39:04 +00:00
|
|
|
config RAM
|
|
|
|
bool "Enable RAM drivers using Driver Model"
|
|
|
|
depends on DM
|
|
|
|
help
|
|
|
|
This allows drivers to be provided for SDRAM and other RAM
|
|
|
|
controllers and their type to be specified in the board's device
|
|
|
|
tree. Generally some parameters are required to set up the RAM and
|
|
|
|
the RAM size can either be statically defined or dynamically
|
|
|
|
detected.
|
|
|
|
|
2015-08-11 22:31:48 +00:00
|
|
|
config SPL_RAM
|
2015-06-23 21:39:04 +00:00
|
|
|
bool "Enable RAM support in SPL"
|
2017-06-28 23:41:52 +00:00
|
|
|
depends on RAM && SPL_DM
|
2015-06-23 21:39:04 +00:00
|
|
|
help
|
|
|
|
The RAM subsystem adds a small amount of overhead to the image.
|
|
|
|
If this is acceptable and you have a need to use RAM drivers in
|
|
|
|
SPL, enable this option. It might provide a cleaner interface to
|
|
|
|
setting up RAM (e.g. SDRAM / DDR) within SPL.
|
2017-04-10 22:02:51 +00:00
|
|
|
|
2017-06-28 23:42:40 +00:00
|
|
|
config TPL_RAM
|
2017-08-25 14:46:00 +00:00
|
|
|
bool "Enable RAM support in TPL"
|
2022-06-08 12:24:39 +00:00
|
|
|
depends on RAM && TPL
|
2017-06-28 23:42:40 +00:00
|
|
|
help
|
|
|
|
The RAM subsystem adds a small amount of overhead to the image.
|
|
|
|
If this is acceptable and you have a need to use RAM drivers in
|
|
|
|
TPL, enable this option. It might provide a cleaner interface to
|
|
|
|
setting up RAM (e.g. SDRAM / DDR) within TPL.
|
|
|
|
|
2017-04-10 22:02:51 +00:00
|
|
|
config STM32_SDRAM
|
|
|
|
bool "Enable STM32 SDRAM support"
|
|
|
|
depends on RAM
|
|
|
|
help
|
|
|
|
STM32F7 family devices support flexible memory controller(FMC) to
|
|
|
|
support external memories like sdram, psram & nand.
|
|
|
|
This driver is for the sdram memory interface with the FMC.
|
2018-03-12 09:46:11 +00:00
|
|
|
|
2018-08-06 08:23:30 +00:00
|
|
|
config MPC83XX_SDRAM
|
|
|
|
bool "Enable MPC83XX SDRAM support"
|
|
|
|
depends on RAM
|
|
|
|
help
|
|
|
|
Enable support for the internal DDR Memory Controller of the MPC83xx
|
|
|
|
family of SoCs. Both static configurations, as well as configuring
|
|
|
|
the RAM through the use of SPD (Serial Presence Detect) is supported
|
|
|
|
via device tree settings.
|
|
|
|
|
2018-11-02 14:21:02 +00:00
|
|
|
config K3_AM654_DDRSS
|
|
|
|
bool "Enable AM654 DDRSS support"
|
|
|
|
depends on RAM && SOC_K3_AM6
|
|
|
|
help
|
|
|
|
K3 based AM654 devices has DDR memory subsystem that comprises
|
|
|
|
Synopys DDR controller, Synopsis DDR phy and wrapper logic to
|
|
|
|
intergrate these blocks into the device. This DDR subsystem
|
|
|
|
provides an interface to external SDRAM devices. Enabling this
|
|
|
|
config add support for the initialization of the external
|
|
|
|
SDRAM devices connected to DDR subsystem.
|
|
|
|
|
2021-05-11 15:22:10 +00:00
|
|
|
config K3_DDRSS
|
|
|
|
bool "Enable K3 DDRSS support"
|
|
|
|
depends on RAM
|
|
|
|
|
|
|
|
choice
|
|
|
|
depends on K3_DDRSS
|
|
|
|
prompt "K3 DDRSS Arch Support"
|
|
|
|
|
2022-01-25 15:26:35 +00:00
|
|
|
default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
|
2021-05-11 15:22:12 +00:00
|
|
|
default K3_AM64_DDRSS if SOC_K3_AM642
|
arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.
Some highlights of this SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
enabling battery powered system design.
AM625 is the first device of the family. Add DT bindings for the same.
More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-05-25 08:08:42 +00:00
|
|
|
default K3_AM64_DDRSS if SOC_K3_AM625
|
2021-05-11 15:22:12 +00:00
|
|
|
|
2019-10-07 13:56:36 +00:00
|
|
|
config K3_J721E_DDRSS
|
|
|
|
bool "Enable J721E DDRSS support"
|
|
|
|
help
|
|
|
|
The J721E DDR subsystem comprises DDR controller, DDR PHY and
|
|
|
|
wrapper logic to integrate these blocks in the device. The DDR
|
|
|
|
subsystem is used to provide an interface to external SDRAM
|
|
|
|
devices which can be utilized for storing program or data.
|
|
|
|
Enabling this config adds support for the DDR memory controller
|
|
|
|
on J721E family of SoCs.
|
|
|
|
|
2021-05-11 15:22:12 +00:00
|
|
|
config K3_AM64_DDRSS
|
|
|
|
bool "Enable AM64 DDRSS support"
|
|
|
|
help
|
|
|
|
The AM64 DDR subsystem comprises DDR controller, DDR PHY and
|
|
|
|
wrapper logic to integrate these blocks in the device. The DDR
|
|
|
|
subsystem is used to provide an interface to external SDRAM
|
|
|
|
devices which can be utilized for storing program or data.
|
|
|
|
Enabling this config adds support for the DDR memory controller
|
|
|
|
on AM642 family of SoCs.
|
|
|
|
|
2021-05-11 15:22:10 +00:00
|
|
|
endchoice
|
|
|
|
|
2020-01-10 14:51:44 +00:00
|
|
|
config IMXRT_SDRAM
|
|
|
|
bool "Enable i.MXRT SDRAM support"
|
|
|
|
depends on RAM
|
|
|
|
help
|
|
|
|
i.MXRT family devices support smart external memory controller(SEMC)
|
|
|
|
to support external memories like sdram, psram & nand.
|
|
|
|
This driver is for the sdram memory interface with the SEMC.
|
|
|
|
|
2020-09-07 08:25:07 +00:00
|
|
|
source "drivers/ram/aspeed/Kconfig"
|
2019-07-15 18:28:46 +00:00
|
|
|
source "drivers/ram/rockchip/Kconfig"
|
2020-05-29 06:03:26 +00:00
|
|
|
source "drivers/ram/sifive/Kconfig"
|
2018-03-12 09:46:11 +00:00
|
|
|
source "drivers/ram/stm32mp1/Kconfig"
|
2020-09-02 06:29:08 +00:00
|
|
|
source "drivers/ram/octeon/Kconfig"
|