2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2017-03-27 17:22:32 +00:00
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/*
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* Allwinner DW HDMI bridge
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*
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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2022-11-28 07:02:27 +00:00
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#include <clk.h>
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2017-03-27 17:22:32 +00:00
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <dw_hdmi.h>
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#include <edid.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2022-11-28 07:02:27 +00:00
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#include <reset.h>
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2019-11-14 19:57:30 +00:00
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#include <time.h>
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2017-03-27 17:22:32 +00:00
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lcdc.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2022-11-28 07:02:28 +00:00
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#include <power/regulator.h>
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2017-03-27 17:22:32 +00:00
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struct sunxi_dw_hdmi_priv {
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struct dw_hdmi hdmi;
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2022-11-28 07:02:27 +00:00
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struct reset_ctl_bulk resets;
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struct clk_bulk clocks;
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2022-11-28 07:02:28 +00:00
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struct udevice *hvcc;
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2017-03-27 17:22:32 +00:00
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};
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struct sunxi_hdmi_phy {
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u32 pol;
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u32 res1[3];
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u32 read_en;
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u32 unscramble;
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u32 res2[2];
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u32 ctrl;
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u32 unk1;
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u32 unk2;
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u32 pll;
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u32 clk;
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u32 unk3;
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u32 status;
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};
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#define HDMI_PHY_OFFS 0x10000
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static int sunxi_dw_hdmi_get_divider(uint clock)
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{
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/*
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* Due to missing documentaion of HDMI PHY, we know correct
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* settings only for following four PHY dividers. Select one
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* based on clock speed.
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*/
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if (clock <= 27000000)
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return 11;
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else if (clock <= 74250000)
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return 4;
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else if (clock <= 148500000)
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return 2;
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else
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return 1;
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}
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2022-11-28 07:02:26 +00:00
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static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
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2017-03-27 17:22:32 +00:00
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{
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struct sunxi_hdmi_phy * const phy =
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2022-11-28 07:02:26 +00:00
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(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
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2017-03-27 17:22:32 +00:00
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unsigned long tmo;
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u32 tmp;
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/*
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* HDMI PHY settings are taken as-is from Allwinner BSP code.
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* There is no documentation.
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*/
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writel(0, &phy->ctrl);
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setbits_le32(&phy->ctrl, BIT(0));
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udelay(5);
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setbits_le32(&phy->ctrl, BIT(16));
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setbits_le32(&phy->ctrl, BIT(1));
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udelay(10);
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setbits_le32(&phy->ctrl, BIT(2));
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udelay(5);
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setbits_le32(&phy->ctrl, BIT(3));
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udelay(40);
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setbits_le32(&phy->ctrl, BIT(19));
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udelay(100);
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setbits_le32(&phy->ctrl, BIT(18));
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setbits_le32(&phy->ctrl, 7 << 4);
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/* Note that Allwinner code doesn't fail in case of timeout */
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tmo = timer_get_us() + 2000;
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while ((readl(&phy->status) & 0x80) == 0) {
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if (timer_get_us() > tmo) {
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printf("Warning: HDMI PHY init timeout!\n");
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break;
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}
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}
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setbits_le32(&phy->ctrl, 0xf << 8);
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setbits_le32(&phy->ctrl, BIT(7));
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writel(0x39dc5040, &phy->pll);
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writel(0x80084343, &phy->clk);
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udelay(10000);
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writel(1, &phy->unk3);
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setbits_le32(&phy->pll, BIT(25));
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udelay(100000);
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tmp = (readl(&phy->status) & 0x1f800) >> 11;
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setbits_le32(&phy->pll, BIT(31) | BIT(30));
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setbits_le32(&phy->pll, tmp);
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writel(0x01FF0F7F, &phy->ctrl);
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writel(0x80639000, &phy->unk1);
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writel(0x0F81C405, &phy->unk2);
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/* enable read access to HDMI controller */
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writel(0x54524545, &phy->read_en);
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/* descramble register offsets */
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writel(0x42494E47, &phy->unscramble);
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}
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2022-11-28 07:02:26 +00:00
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static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
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2017-03-27 17:22:32 +00:00
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{
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struct sunxi_hdmi_phy * const phy =
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2022-11-28 07:02:26 +00:00
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(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
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2017-03-27 17:22:32 +00:00
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int div = sunxi_dw_hdmi_get_divider(clock);
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u32 tmp;
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/*
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* Unfortunately, we don't know much about those magic
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* numbers. They are taken from Allwinner BSP driver.
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*/
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switch (div) {
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case 1:
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writel(0x30dc5fc0, &phy->pll);
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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writel(0x800863C0 | (phy_div - 1), &phy->clk);
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2017-03-27 17:22:32 +00:00
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mdelay(10);
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writel(0x00000001, &phy->unk3);
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setbits_le32(&phy->pll, BIT(25));
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mdelay(200);
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tmp = (readl(&phy->status) & 0x1f800) >> 11;
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setbits_le32(&phy->pll, BIT(31) | BIT(30));
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if (tmp < 0x3d)
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setbits_le32(&phy->pll, tmp + 2);
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else
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setbits_le32(&phy->pll, 0x3f);
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mdelay(100);
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writel(0x01FFFF7F, &phy->ctrl);
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writel(0x8063b000, &phy->unk1);
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writel(0x0F8246B5, &phy->unk2);
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break;
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case 2:
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writel(0x39dc5040, &phy->pll);
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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writel(0x80084380 | (phy_div - 1), &phy->clk);
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2017-03-27 17:22:32 +00:00
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mdelay(10);
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writel(0x00000001, &phy->unk3);
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setbits_le32(&phy->pll, BIT(25));
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mdelay(100);
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tmp = (readl(&phy->status) & 0x1f800) >> 11;
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setbits_le32(&phy->pll, BIT(31) | BIT(30));
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setbits_le32(&phy->pll, tmp);
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writel(0x01FFFF7F, &phy->ctrl);
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writel(0x8063a800, &phy->unk1);
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writel(0x0F81C485, &phy->unk2);
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break;
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case 4:
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writel(0x39dc5040, &phy->pll);
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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writel(0x80084340 | (phy_div - 1), &phy->clk);
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2017-03-27 17:22:32 +00:00
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mdelay(10);
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writel(0x00000001, &phy->unk3);
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setbits_le32(&phy->pll, BIT(25));
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mdelay(100);
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tmp = (readl(&phy->status) & 0x1f800) >> 11;
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setbits_le32(&phy->pll, BIT(31) | BIT(30));
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setbits_le32(&phy->pll, tmp);
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writel(0x01FFFF7F, &phy->ctrl);
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writel(0x8063b000, &phy->unk1);
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writel(0x0F81C405, &phy->unk2);
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break;
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case 11:
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writel(0x39dc5040, &phy->pll);
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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writel(0x80084300 | (phy_div - 1), &phy->clk);
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2017-03-27 17:22:32 +00:00
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mdelay(10);
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writel(0x00000001, &phy->unk3);
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setbits_le32(&phy->pll, BIT(25));
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mdelay(100);
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tmp = (readl(&phy->status) & 0x1f800) >> 11;
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setbits_le32(&phy->pll, BIT(31) | BIT(30));
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setbits_le32(&phy->pll, tmp);
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writel(0x01FFFF7F, &phy->ctrl);
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writel(0x8063b000, &phy->unk1);
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writel(0x0F81C405, &phy->unk2);
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break;
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}
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}
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
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2017-03-27 17:22:32 +00:00
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{
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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int value, n, m, div, diff;
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int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
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2017-03-27 17:22:32 +00:00
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/*
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* Find the lowest divider resulting in a matching clock. If there
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* is no match, pick the closest lower clock, as monitors tend to
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* not sync to higher frequencies.
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*/
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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for (div = 1; div <= 16; div++) {
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int target = clk_khz * div;
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if (target < 192000)
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continue;
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if (target > 912000)
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continue;
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for (m = 1; m <= 16; m++) {
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n = (m * target) / 24000;
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if (n >= 1 && n <= 128) {
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value = (24000 * n) / m / div;
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diff = clk_khz - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_m = m;
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best_n = n;
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best_div = div;
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}
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2017-03-27 17:22:32 +00:00
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}
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}
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}
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|
sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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*phy_div = best_div;
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2017-03-27 17:22:32 +00:00
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clock_set_pll3_factors(best_m, best_n);
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debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
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sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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clk_khz, (clock_get_pll3() / 1000) / best_div,
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best_n, best_m, best_div);
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2017-03-27 17:22:32 +00:00
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}
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static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
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int bpp)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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2019-08-09 20:30:26 +00:00
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int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
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2017-03-27 17:22:32 +00:00
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struct sunxi_lcdc_reg *lcdc;
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if (mux == 0) {
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lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
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/* Reset off */
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
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/* Clock on */
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
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writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
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&ccm->lcd0_clk_cfg);
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} else {
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lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
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/* Reset off */
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
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/* Clock on */
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
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writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
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&ccm->lcd1_clk_cfg);
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}
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lcdc_init(lcdc);
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lcdc_tcon1_mode_set(lcdc, edid, false, false);
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lcdc_enable(lcdc, bpp);
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}
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static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
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{
|
sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.
The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.
With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.
Fixes: 56009451d843 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-24 18:26:40 +00:00
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int phy_div;
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sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
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2022-11-28 07:02:26 +00:00
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sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
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2017-03-27 17:22:32 +00:00
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return 0;
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}
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static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
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{
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struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
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}
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2021-04-22 00:14:26 +00:00
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static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
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const struct display_timing *timing)
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{
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return timing->pixelclock.typ <= 297000000;
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}
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2017-03-27 17:22:32 +00:00
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static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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2022-11-28 07:02:26 +00:00
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struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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2017-03-27 17:22:32 +00:00
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struct sunxi_hdmi_phy * const phy =
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2022-11-28 07:02:26 +00:00
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(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
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2021-04-22 00:14:33 +00:00
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struct display_plat *uc_plat = dev_get_uclass_plat(dev);
|
2017-03-27 17:22:32 +00:00
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int ret;
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ret = dw_hdmi_enable(&priv->hdmi, edid);
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if (ret)
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return ret;
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2021-04-22 00:14:33 +00:00
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sunxi_dw_hdmi_lcdc_init(uc_plat->source_id, edid, panel_bpp);
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2017-03-27 17:22:32 +00:00
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2018-05-14 20:49:52 +00:00
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if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
|
2017-11-29 06:33:27 +00:00
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setbits_le32(&phy->pol, 0x200);
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2018-05-14 20:49:52 +00:00
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if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
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2017-11-29 06:33:27 +00:00
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setbits_le32(&phy->pol, 0x100);
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2017-03-27 17:22:32 +00:00
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setbits_le32(&phy->ctrl, 0xf << 12);
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|
/*
|
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* This is last hdmi access before boot, so scramble addresses
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* again or othwerwise BSP driver won't work. Dummy read is
|
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* needed or otherwise last write doesn't get written correctly.
|
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*/
|
2022-11-28 07:02:26 +00:00
|
|
|
(void)readb(priv->hdmi.ioaddr);
|
2017-03-27 17:22:32 +00:00
|
|
|
writel(0, &phy->unscramble);
|
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|
return 0;
|
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|
}
|
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|
|
static int sunxi_dw_hdmi_probe(struct udevice *dev)
|
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|
{
|
|
|
|
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
|
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
int ret;
|
|
|
|
|
2022-11-28 07:02:28 +00:00
|
|
|
if (priv->hvcc)
|
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|
|
regulator_set_enable(priv->hvcc, true);
|
|
|
|
|
2017-03-27 17:22:32 +00:00
|
|
|
/* Set pll3 to 297 MHz */
|
|
|
|
clock_set_pll3(297000000);
|
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|
|
|
|
|
|
/* Set hdmi parent to pll3 */
|
|
|
|
clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
|
|
|
|
CCM_HDMI_CTRL_PLL3);
|
|
|
|
|
2022-11-28 07:02:27 +00:00
|
|
|
/* This reset is referenced from the PHY devicetree node. */
|
2017-03-27 17:22:32 +00:00
|
|
|
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
|
|
|
|
|
2022-11-28 07:02:27 +00:00
|
|
|
ret = reset_deassert_bulk(&priv->resets);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_enable_bulk(&priv->clocks);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2017-03-27 17:22:32 +00:00
|
|
|
|
2022-11-28 07:02:26 +00:00
|
|
|
sunxi_dw_hdmi_phy_init(&priv->hdmi);
|
2017-03-27 17:22:32 +00:00
|
|
|
|
2021-04-22 00:14:30 +00:00
|
|
|
ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
|
|
|
|
if (ret < 0) {
|
|
|
|
debug("hdmi can not get hpd signal\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2017-03-27 17:22:32 +00:00
|
|
|
dw_hdmi_init(&priv->hdmi);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-11-28 07:02:26 +00:00
|
|
|
static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
|
|
|
|
struct dw_hdmi *hdmi = &priv->hdmi;
|
2022-11-28 07:02:27 +00:00
|
|
|
int ret;
|
2022-11-28 07:02:26 +00:00
|
|
|
|
|
|
|
hdmi->ioaddr = (ulong)dev_read_addr(dev);
|
|
|
|
hdmi->i2c_clk_high = 0xd8;
|
|
|
|
hdmi->i2c_clk_low = 0xfe;
|
|
|
|
hdmi->reg_io_width = 1;
|
|
|
|
hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
|
|
|
|
|
2022-11-28 07:02:27 +00:00
|
|
|
ret = reset_get_bulk(dev, &priv->resets);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_get_bulk(dev, &priv->clocks);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2022-11-28 07:02:28 +00:00
|
|
|
ret = device_get_supply_regulator(dev, "hvcc-supply", &priv->hvcc);
|
|
|
|
if (ret)
|
|
|
|
priv->hvcc = NULL;
|
|
|
|
|
2022-11-28 07:02:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-03-27 17:22:32 +00:00
|
|
|
static const struct dm_display_ops sunxi_dw_hdmi_ops = {
|
|
|
|
.read_edid = sunxi_dw_hdmi_read_edid,
|
|
|
|
.enable = sunxi_dw_hdmi_enable,
|
2021-04-22 00:14:26 +00:00
|
|
|
.mode_valid = sunxi_dw_hdmi_mode_valid,
|
2017-03-27 17:22:32 +00:00
|
|
|
};
|
|
|
|
|
2022-11-28 07:02:25 +00:00
|
|
|
static const struct udevice_id sunxi_dw_hdmi_ids[] = {
|
|
|
|
{ .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
|
|
|
|
{ }
|
2017-03-27 17:22:32 +00:00
|
|
|
};
|
|
|
|
|
2022-11-28 07:02:25 +00:00
|
|
|
U_BOOT_DRIVER(sunxi_dw_hdmi) = {
|
|
|
|
.name = "sunxi_dw_hdmi",
|
|
|
|
.id = UCLASS_DISPLAY,
|
|
|
|
.of_match = sunxi_dw_hdmi_ids,
|
|
|
|
.probe = sunxi_dw_hdmi_probe,
|
2022-11-28 07:02:26 +00:00
|
|
|
.of_to_plat = sunxi_dw_hdmi_of_to_plat,
|
2022-11-28 07:02:25 +00:00
|
|
|
.priv_auto = sizeof(struct sunxi_dw_hdmi_priv),
|
|
|
|
.ops = &sunxi_dw_hdmi_ops,
|
2017-03-27 17:22:32 +00:00
|
|
|
};
|