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sunxi: video: HDMI: split VSYNC and HSYNC polarity settings

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These are actually different bits, and since some monitors (Benq BL2420PT)
have modes with different HSYNC and VSYNC polarity, we should set them
independently

Tested on Pine64-LTS with Benq BL2420PT monitor.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Vasily Khoruzhick 2017-11-28 22:33:27 -08:00 committed by Jagan Teki
parent 3cfecee49c
commit 6408917821
1 changed files with 5 additions and 9 deletions
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14
drivers/video/sunxi/sunxi_dw_hdmi.c
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@ -304,15 +304,11 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
/*
* Condition in original code is a bit weird. This is attempt
* to make it more reasonable and it works. It could be that
* bits and conditions are related and should be separated.
*/
if (!((edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) &&
(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH))) {
setbits_le32(&phy->pol, 0x300);
}
if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
setbits_le32(&phy->pol, 0x200);
if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
setbits_le32(&phy->pol, 0x100);
setbits_le32(&phy->ctrl, 0xf << 12);