2018-05-06 21:58:06 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2013-12-06 20:30:23 +00:00
|
|
|
/*
|
|
|
|
* ti_omap3_common.h
|
|
|
|
*
|
2023-11-01 20:56:03 +00:00
|
|
|
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
|
2013-12-06 20:30:23 +00:00
|
|
|
*
|
|
|
|
* For more details, please see the technical documents listed at
|
2023-11-01 20:56:03 +00:00
|
|
|
* https://www.ti.com/product/omap3530
|
|
|
|
* https://www.ti.com/product/omap3630
|
|
|
|
* https://www.ti.com/product/dm3730
|
2013-12-06 20:30:23 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
|
|
|
|
#define __CONFIG_TI_OMAP3_COMMON_H__
|
|
|
|
|
2016-01-27 07:46:11 +00:00
|
|
|
/*
|
|
|
|
* High Level Configuration Options
|
|
|
|
*/
|
|
|
|
|
2013-12-06 20:30:23 +00:00
|
|
|
#include <asm/arch/cpu.h>
|
2015-03-09 22:12:04 +00:00
|
|
|
#include <asm/arch/omap.h>
|
2013-12-06 20:30:23 +00:00
|
|
|
|
|
|
|
/* Clock Defines */
|
|
|
|
#define V_OSCK 26000000 /* Clock output from T2 */
|
|
|
|
#define V_SCLK (V_OSCK >> 1)
|
|
|
|
|
|
|
|
/* NS16550 Configuration */
|
|
|
|
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
2022-11-16 18:10:28 +00:00
|
|
|
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
|
2013-12-06 20:30:23 +00:00
|
|
|
115200}
|
|
|
|
|
|
|
|
/* Select serial console configuration */
|
2014-10-23 03:37:15 +00:00
|
|
|
#ifdef CONFIG_SPL_BUILD
|
2022-11-16 18:10:28 +00:00
|
|
|
#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1
|
|
|
|
#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2
|
|
|
|
#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
|
2014-10-23 03:37:15 +00:00
|
|
|
#endif
|
2013-12-06 20:30:23 +00:00
|
|
|
|
|
|
|
/* Physical Memory Map */
|
|
|
|
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
|
|
|
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
|
|
|
|
|
|
|
/*
|
|
|
|
* OMAP3 has 12 GP timers, they can be driven by the system clock
|
|
|
|
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
|
|
|
* This rate is divided by a local divisor.
|
|
|
|
*/
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
2013-12-06 20:30:23 +00:00
|
|
|
|
|
|
|
/* SPL */
|
2014-04-03 11:52:53 +00:00
|
|
|
|
2019-10-03 17:50:03 +00:00
|
|
|
#ifdef CONFIG_MTD_RAW_NAND
|
2022-11-12 22:36:51 +00:00
|
|
|
#define CFG_SYS_NAND_BASE 0x30000000
|
2013-12-06 20:30:23 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Now bring in the rest of the common code. */
|
2015-07-22 23:05:41 +00:00
|
|
|
#include <configs/ti_armv7_omap.h>
|
2013-12-06 20:30:23 +00:00
|
|
|
|
|
|
|
#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */
|