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u-boot/arch/arm/mach-k3/Makefile

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arm: K3: Add support for AM654 SoC definition The AM654 device is designed for industrial automation and PLC controller class platforms among other applications. Introduce base support for AM654 SoC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-08-27 10:27:09 +00:00
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
arm: mach-k3: Add platform data for j721e and j7200 Add platform clock and powerdomain data for J721e and J7200. This data is used by the corresponding drivers to register all the required device clocks and powerdomains. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:18 +00:00
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
arm: K3: Add basic support for J721S2 SoC definition Add basic support for J721S2 SoC definition Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-01-25 15:26:31 +00:00
obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
arm: mach-k3: Add basic support for AM642 SoC definition The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:32 +00:00
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
obj-$(CONFIG_ARM64) += arm64-mmu.o
armv7r: K3: Allow SPL to run only on core 0 Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-11-15 05:34:50 +00:00
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
arm: mach-k3: Add secure device support K3 devices have High Security (HS) variants along with the non-HS already supported. Like the previous generation devices (OMAP/Keystone2) K3 supports boot chain-of-trust by authenticating and optionally decrypting images as they are unpacked from FIT images. Add support for this here. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-12 16:54:45 +00:00
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
arm: mach-k3: Clean non-coherent lines out of L3 cache When switching on or off the ARM caches some care must be taken to ensure existing cache line allocations are not left in an inconsistent state. An example of this is when cache lines are considered non-shared by and L3 controller even though the lines are shared. To prevent these and other issues all cache lines should be cleared before enabling or disabling a coherent master's cache. ARM cores and many L3 controllers provide a way to efficiently clean out all cache lines to allow for this, unfortunately there is no such easy way to do this on current K3 MSMC based systems. We could explicitly clean out every valid external address tracked by MSMC (all of DRAM), or we could attempt to identify only the set of addresses accessed by a given boot stage and flush only those specifically. This patch attempts the latter. We start with cleaning the SPL load address. More addresses can be added here later as they are identified. Note that we perform a flush operation for both the flush and invalidate operations, this is not a typo. We do this to avoid the situation that some ARM cores will promote an invalidate to a clean+invalidate, but only emit the invalidation operation externally, leading to a loss of data. Signed-off-by: Andrew F. Davis <afd@ti.com> Tested-by: Faiz Abbas <faiz_abbas@ti.com>
2020-07-15 21:02:36 +00:00
obj-$(CONFIG_ARM64) += cache.o
arm: K3: Introduce System Firmware loader framework Introduce a framework that allows loading the System Firmware (SYSFW) binary as well as the associated configuration data from an image tree blob named "sysfw.itb" from an FS-based MMC boot media or from an MMC RAW mode partition or sector. To simplify the handling of and loading from the different boot media we tap into the existing U-Boot SPL framework usually used for loading U-Boot by building on an earlier commit that exposes some of that functionality. Note that this initial implementation only supports FS and RAW-based eMMC/SD card boot. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-04 22:55:47 +00:00
ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
armv7R: K3: am654: Add support to start ATF from R5 SPL Considering the boot time requirements, Cortex-A core should be able to start immediately after SPL on R5. Add support for the same. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-11-02 14:21:05 +00:00
obj-y += common.o
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