2016-07-22 04:38:31 +00:00
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/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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2016-08-10 07:08:36 +00:00
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#include <linux/kernel.h>
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2016-07-22 04:38:31 +00:00
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#include <asm/armv7.h>
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2016-08-10 07:08:36 +00:00
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#include <asm/processor.h>
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2016-07-22 04:38:31 +00:00
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#include "ssc-regs.h"
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2016-08-10 07:08:36 +00:00
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#define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
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((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
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2016-07-22 04:38:31 +00:00
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#ifdef CONFIG_UNIPHIER_L2CACHE_ON
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/* uniphier_cache_sync - perform a sync point for a particular cache level */
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2016-07-22 04:38:31 +00:00
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static void uniphier_cache_sync(void)
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{
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/* drain internal buffers */
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writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
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/* need a read back to confirm */
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readl(UNIPHIER_SSCOPE);
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}
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2016-08-10 07:08:36 +00:00
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/**
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* uniphier_cache_maint_common - run a queue operation
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*
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* @start: start address of range operation (don't care for "all" operation)
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* @size: data size of range operation (don't care for "all" operation)
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* @operation: flags to specify the desired cache operation
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*/
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static void uniphier_cache_maint_common(u32 start, u32 size, u32 operation)
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{
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/* clear the complete notification flag */
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writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
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do {
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/* set cache operation */
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writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM);
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/* set address range if needed */
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if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) {
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writel(start, UNIPHIER_SSCOQAD);
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writel(size, UNIPHIER_SSCOQSZ);
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}
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} while (unlikely(readl(UNIPHIER_SSCOPPQSEF) &
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(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
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/* wait until the operation is completed */
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while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF))
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cpu_relax();
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}
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static void uniphier_cache_maint_all(u32 operation)
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{
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uniphier_cache_maint_common(0, 0, UNIPHIER_SSCOQM_S_ALL | operation);
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uniphier_cache_sync();
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}
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static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
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{
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u32 size;
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/*
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* If the start address is not aligned,
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* perform a cache operation for the first cache-line
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*/
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start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
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size = end - start;
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if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
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/* this means cache operation for all range */
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uniphier_cache_maint_all(operation);
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return;
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}
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/*
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* If the end address is not aligned,
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* perform a cache operation for the last cache-line
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*/
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size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
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while (size) {
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u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE);
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uniphier_cache_maint_common(start, chunk_size,
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UNIPHIER_SSCOQM_S_RANGE | operation);
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start += chunk_size;
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size -= chunk_size;
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}
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uniphier_cache_sync();
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}
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2016-08-10 07:08:36 +00:00
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void v7_outer_cache_flush_all(void)
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{
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uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
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}
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void v7_outer_cache_inval_all(void)
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{
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uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
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}
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void v7_outer_cache_flush_range(u32 start, u32 end)
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{
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uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);
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}
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void v7_outer_cache_inval_range(u32 start, u32 end)
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{
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if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
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start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
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uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE,
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UNIPHIER_SSCOQM_CM_FLUSH);
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start += UNIPHIER_SSC_LINE_SIZE;
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}
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if (start >= end) {
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uniphier_cache_sync();
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return;
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}
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if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
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end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
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uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE,
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UNIPHIER_SSCOQM_CM_FLUSH);
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}
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if (start >= end) {
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uniphier_cache_sync();
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return;
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}
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uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);
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}
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void v7_outer_cache_enable(void)
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{
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u32 tmp;
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writel(U32_MAX, UNIPHIER_SSCLPDAWCR); /* activate all ways */
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tmp = readl(UNIPHIER_SSCC);
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tmp |= UNIPHIER_SSCC_ON;
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writel(tmp, UNIPHIER_SSCC);
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}
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#endif
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void v7_outer_cache_disable(void)
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{
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u32 tmp;
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tmp = readl(UNIPHIER_SSCC);
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tmp &= ~UNIPHIER_SSCC_ON;
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writel(tmp, UNIPHIER_SSCC);
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}
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void enable_caches(void)
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{
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dcache_enable();
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}
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