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u-boot/drivers/clk/sunxi/clk_sunxi.c

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clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Amarula Solutions.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
sunxi: clk: enable clk and reset for CCU devices Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:08 +00:00
#include <reset.h>
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
#include <asm/io.h>
clk: sunxi: Move header out of arch directory The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 16:48:43 +00:00
#include <clk/sunxi.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
#include <linux/log2.h>
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
unsigned long id)
{
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
if (id >= plat->desc->num_gates)
clk: sunxi: Prevent out-of-bounds gate array access Because the gate arrays are not given explicit sizes, the arrays are only as large as the highest-numbered gate described in the driver. However, only a subset of the CCU clocks are needed by U-Boot. So there are valid clock specifiers with indexes greater than the size of the arrays. Referencing any of these clocks causes out-of-bounds access. Fix this by checking the identifier against the size of the array. Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:32 +00:00
return NULL;
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
return &plat->desc->gates[id];
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
}
static int sunxi_set_gate(struct clk *clk, bool on)
{
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
struct ccu_plat *plat = dev_get_plat(clk->dev);
const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
u32 reg;
clk: sunxi: Prevent out-of-bounds gate array access Because the gate arrays are not given explicit sizes, the arrays are only as large as the highest-numbered gate described in the driver. However, only a subset of the CCU clocks are needed by U-Boot. So there are valid clock specifiers with indexes greater than the size of the arrays. Referencing any of these clocks causes out-of-bounds access. Fix this by checking the identifier against the size of the array. Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:32 +00:00
if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
clk: sunxi: add and use dummy gate clocks Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-05 00:25:43 +00:00
return 0;
clk: sunxi: Prevent out-of-bounds gate array access Because the gate arrays are not given explicit sizes, the arrays are only as large as the highest-numbered gate described in the driver. However, only a subset of the CCU clocks are needed by U-Boot. So there are valid clock specifiers with indexes greater than the size of the arrays. Referencing any of these clocks causes out-of-bounds access. Fix this by checking the identifier against the size of the array. Fixes: 0d47bc705651 ("clk: Add Allwinner A64 CLK driver") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:32 +00:00
if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
return 0;
}
debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
clk->id, gate->off, ilog2(gate->bit));
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
reg = readl(plat->base + gate->off);
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
if (on)
reg |= gate->bit;
else
reg &= ~gate->bit;
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
writel(reg, plat->base + gate->off);
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
return 0;
}
static int sunxi_clk_enable(struct clk *clk)
{
return sunxi_set_gate(clk, true);
}
static int sunxi_clk_disable(struct clk *clk)
{
return sunxi_set_gate(clk, false);
}
struct clk_ops sunxi_clk_ops = {
.enable = sunxi_clk_enable,
.disable = sunxi_clk_disable,
};
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
static int sunxi_clk_bind(struct udevice *dev)
reset: sunxi: Get the reset count from the CCU descriptor This allows all of the clock drivers to use a common bind function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:33 +00:00
{
return sunxi_reset_bind(dev);
}
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
static int sunxi_clk_probe(struct udevice *dev)
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
{
sunxi: clk: enable clk and reset for CCU devices Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:08 +00:00
struct clk_bulk clk_bulk;
struct reset_ctl_bulk rst_bulk;
int ret;
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
sunxi: clk: enable clk and reset for CCU devices Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:08 +00:00
ret = clk_get_bulk(dev, &clk_bulk);
if (!ret)
clk_enable_bulk(&clk_bulk);
ret = reset_get_bulk(dev, &rst_bulk);
if (!ret)
reset_deassert_bulk(&rst_bulk);
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
return 0;
}
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
static int sunxi_clk_of_to_plat(struct udevice *dev)
{
struct ccu_plat *plat = dev_get_plat(dev);
plat->base = dev_read_addr_ptr(dev);
if (!plat->base)
return -ENOMEM;
plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
if (!plat->desc)
return -EINVAL;
return 0;
}
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
extern const struct ccu_desc a10_ccu_desc;
extern const struct ccu_desc a10s_ccu_desc;
extern const struct ccu_desc a23_ccu_desc;
extern const struct ccu_desc a31_ccu_desc;
extern const struct ccu_desc a31_r_ccu_desc;
extern const struct ccu_desc a64_ccu_desc;
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
extern const struct ccu_desc h616_ccu_desc;
extern const struct ccu_desc h6_r_ccu_desc;
extern const struct ccu_desc r40_ccu_desc;
extern const struct ccu_desc v3s_ccu_desc;
static const struct udevice_id sunxi_clk_ids[] = {
#ifdef CONFIG_CLK_SUN4I_A10
{ .compatible = "allwinner,sun4i-a10-ccu",
.data = (ulong)&a10_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN5I_A10S
{ .compatible = "allwinner,sun5i-a10s-ccu",
.data = (ulong)&a10s_ccu_desc },
{ .compatible = "allwinner,sun5i-a13-ccu",
.data = (ulong)&a10s_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31
{ .compatible = "allwinner,sun6i-a31-ccu",
.data = (ulong)&a31_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN4I_A10
{ .compatible = "allwinner,sun7i-a20-ccu",
.data = (ulong)&a10_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_A23
{ .compatible = "allwinner,sun8i-a23-ccu",
.data = (ulong)&a23_ccu_desc },
{ .compatible = "allwinner,sun8i-a33-ccu",
.data = (ulong)&a23_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_A83T
{ .compatible = "allwinner,sun8i-a83t-ccu",
.data = (ulong)&a83t_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun8i-a83t-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_H3
{ .compatible = "allwinner,sun8i-h3-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun8i-h3-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_R40
{ .compatible = "allwinner,sun8i-r40-ccu",
.data = (ulong)&r40_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_V3S
{ .compatible = "allwinner,sun8i-v3-ccu",
.data = (ulong)&v3s_ccu_desc },
{ .compatible = "allwinner,sun8i-v3s-ccu",
.data = (ulong)&v3s_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN9I_A80
{ .compatible = "allwinner,sun9i-a80-ccu",
.data = (ulong)&a80_ccu_desc },
{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
.data = (ulong)&a80_mmc_clk_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_A64
{ .compatible = "allwinner,sun50i-a64-ccu",
.data = (ulong)&a64_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun50i-a64-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_H3
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6_R
{ .compatible = "allwinner,sun50i-h6-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H616
{ .compatible = "allwinner,sun50i-h616-ccu",
.data = (ulong)&h616_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6_R
{ .compatible = "allwinner,sun50i-h616-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUNIV_F1C100S
{ .compatible = "allwinner,suniv-f1c100s-ccu",
.data = (ulong)&f1c100s_ccu_desc },
#endif
{ }
};
U_BOOT_DRIVER(sunxi_clk) = {
.name = "sunxi_clk",
.id = UCLASS_CLK,
.of_match = sunxi_clk_ids,
.bind = sunxi_clk_bind,
.probe = sunxi_clk_probe,
clk: sunxi: Convert driver private data to platform data All of the driver private data should really be platform data since it is determined statically (selected by the compatible string or extracted from the devicetree). Move everything to platform data, so it can be provided when binding the driver. This is useful for SPL, or for instantiating the driver as part of an MFD. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:35 +00:00
.of_to_plat = sunxi_clk_of_to_plat,
.plat_auto = sizeof(struct ccu_plat),
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
.ops = &sunxi_clk_ops,
};
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