Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-12-21 18:53:06 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/configs/xilinx_zynqmp_r5_defconfig

30 lines
762 B
Text
Raw Normal View History

arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
CONFIG_ARM=y
Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-28 01:18:30 +00:00
CONFIG_SKIP_LOWLEVEL_INIT=y
arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
CONFIG_ARCH_ZYNQMP_R5=y
CONFIG_SYS_TEXT_BASE=0x10000000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 12:19:22 +00:00
CONFIG_SYS_MALLOC_LEN=0x1400000
xilinx: zynqmp-r5: Increase amount of MALLOC space There is not enough space for early allocation. That's why increase it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-16 11:35:03 +00:00
CONFIG_SYS_MALLOC_F_LEN=0x1000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-29 19:54:04 +00:00
CONFIG_NR_DRAM_BANKS=1
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-08-10 19:31:07 +00:00
CONFIG_ENV_SIZE=0x20000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-06-28 14:17:29 +00:00
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-r5"
xilinx: Sync symbols location in defconfigs CONFIG_DEBUG_UART_BASE and CONFIG_DEBUG_UART_CLOCK have changed that's why this sync. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-04 06:33:30 +00:00
CONFIG_DEBUG_UART_BASE=0xff010000
CONFIG_DEBUG_UART_CLOCK=100000000
Convert CONFIG_CPU_FREQ_HZ to Kconfig This converts the following to Kconfig: CONFIG_CPU_FREQ_HZ Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-17 23:08:42 +00:00
CONFIG_CPU_FREQ_HZ=500000000
Convert CONFIG_SYS_LOAD_ADDR to Kconfig Now that we have consistent usage, migrate this symbol to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-23 14:25:31 +00:00
CONFIG_SYS_LOAD_ADDR=0x0
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08 17:36:51 +00:00
CONFIG_DEBUG_UART=y
timer: cadence: Implement timer_get_boot_us This function is required for adding bootstage support. Also enable it directly for ZynqMP R5 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-18 12:03:56 +00:00
CONFIG_BOOTSTAGE=y
arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SYS_PROMPT="ZynqMP r5> "
Convert CONFIG_SYS_MAXARGS to Kconfig This converts the following to Kconfig: CONFIG_SYS_MAXARGS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-11 20:21:06 +00:00
CONFIG_SYS_MAXARGS=32
Convert CONFIG_SYS_CBSIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_CBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-11 22:01:06 +00:00
CONFIG_SYS_CBSIZE=256
Convert CONFIG_SYS_PBSIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_PBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-11 21:38:09 +00:00
CONFIG_SYS_PBSIZE=284
arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
# CONFIG_CMD_SETEXPR is not set
timer: cadence: Implement timer_get_boot_us This function is required for adding bootstage support. Also enable it directly for ZynqMP R5 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-18 12:03:56 +00:00
CONFIG_CMD_BOOTSTAGE=y
arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
CONFIG_OF_EMBED=y
Convert CONFIG_ENV_OVERWRITE to Kconfig This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-03 11:48:56 +00:00
CONFIG_ENV_OVERWRITE=y
env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol Today in initr_reloc_global_data() we use some non-obvious tests to determine if we need to relocate the env_addr within gd or not. In order to facilitate migration of other symbols to Kconfig we need to introduce a new symbol for this particular use case. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-13 03:46:36 +00:00
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
arm: zynqmp: Add ZynqMP minimal R5 support Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-12 15:39:46 +00:00
CONFIG_ZYNQ_SERIAL=y
CONFIG_TIMER=y
CONFIG_CADENCE_TTC_TIMER=y
xilinx: r5: Disable EFI loader Xilinx ZynqMP R5 configuration is quite minimal and there is no reason to enable EFI for it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-09-14 14:27:56 +00:00
# CONFIG_EFI_LOADER is not set
Reference in a new issue Copy permalink