u-boot/arch/arm/dts/imx6qdl-colibri.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2022 Toradex
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "Toradex Colibri iMX6DL/S Module";
	compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";

	backlight: backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0 45 63 88 119 158 203 255>;
		default-brightness-level = <4>;
		enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		power-supply = <&reg_module_3v3>;
		pwms = <&pwm3 0 5000000 PWM_POLARITY_INVERTED>;
		status = "disabled";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		wakeup {
			debounce-interval = <10>;
			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	lcd_display: disp0 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "bgr666";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu1_lcdif>;
		status = "disabled";

		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			lcd_display_in: endpoint {
				remote-endpoint = <&ipu1_di0_disp0>;
			};
		};

		port@1 {
			reg = <1>;

			lcd_display_out: endpoint {
				remote-endpoint = <&lcd_panel_in>;
			};
		};
	};

	/* Will be filled by the bootloader */
	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0>;
	};

	panel_dpi: panel-dpi {
		/*
		 * edt,et057090dhu: EDT 5.7" LCD TFT
		 * edt,et070080dh6: EDT 7.0" LCD TFT
		 */
		compatible = "edt,et057090dhu";
		backlight = <&backlight>;
		status = "disabled";

		port {
			lcd_panel_in: endpoint {
				remote-endpoint = <&lcd_display_out>;
			};
		};
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_module_3v3_audio: regulator-module-3v3-audio {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb_host_vbus: regulator-usb-host-vbus {
		compatible = "regulator-fixed";
		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb_host_vbus";
		status = "disabled";
	};

	sound {
		compatible = "fsl,imx-audio-sgtl5000";
		audio-codec = <&codec>;
		audio-routing =
			"Headphone Jack", "HP_OUT",
			"LINE_IN", "Line In Jack",
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias";
		model = "imx6dl-colibri-sgtl5000";
		mux-int-port = <1>;
		mux-ext-port = <5>;
		ssi-controller = <&ssi1>;
	};

	/* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
	sound_spdif: sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		spdif-controller = <&spdif>;
		spdif-in;
		spdif-out;
		model = "imx-spdif";
		status = "disabled";
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
	status = "okay";
};

/* Optional on SODIMM 55/63 */
&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

/* Optional on SODIMM 178/188 */
&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
};

&clks {
	fsl,pmic-stby-poweroff;
};

/* Colibri SSP */
&ecspi4 {
	cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi4>;
	status = "disabled";
};

&fec {
	phy-mode = "rmii";
	phy-handle = <&ethphy>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@0 {
			reg = <0>;
			micrel,led-mode = <0>;
		};
	};
};

&gpio1 {
	gpio-line-names = "",
			  "SODIMM_67",
			  "SODIMM_180",
			  "SODIMM_196",
			  "SODIMM_174",
			  "SODIMM_176",
			  "SODIMM_194",
			  "SODIMM_55",
			  "SODIMM_63",
			  "SODIMM_28",
			  "SODIMM_93",
			  "SODIMM_69",
			  "SODIMM_99",
			  "SODIMM_130",
			  "SODIMM_106",
			  "SODIMM_98",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_190",
			  "SODIMM_51",
			  "SODIMM_47",
			  "SODIMM_53",
			  "",
			  "SODIMM_22";
};

&gpio2 {
	gpio-line-names = "SODIMM_132",
			  "SODIMM_134",
			  "SODIMM_135",
			  "SODIMM_133",
			  "SODIMM_102",
			  "SODIMM_43",
			  "SODIMM_127",
			  "SODIMM_37",
			  "SODIMM_104",
			  "SODIMM_59",
			  "SODIMM_30",
			  "SODIMM_100",
			  "SODIMM_38",
			  "SODIMM_34",
			  "SODIMM_32",
			  "SODIMM_36",
			  "SODIMM_59",
			  "SODIMM_67",
			  "SODIMM_97",
			  "SODIMM_79",
			  "SODIMM_103",
			  "SODIMM_101",
			  "SODIMM_45",
			  "SODIMM_105",
			  "SODIMM_107",
			  "SODIMM_91",
			  "SODIMM_89",
			  "SODIMM_150",
			  "SODIMM_126",
			  "SODIMM_128",
			  "",
			  "SODIMM_94";
};

&gpio3 {
	gpio-line-names = "SODIMM_111",
			  "SODIMM_113",
			  "SODIMM_115",
			  "SODIMM_117",
			  "SODIMM_119",
			  "SODIMM_121",
			  "SODIMM_123",
			  "SODIMM_125",
			  "SODIMM_110",
			  "SODIMM_112",
			  "SODIMM_114",
			  "SODIMM_116",
			  "SODIMM_118",
			  "SODIMM_120",
			  "SODIMM_122",
			  "SODIMM_124",
			  "",
			  "SODIMM_96",
			  "SODIMM_77",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_88",
			  "SODIMM_90",
			  "SODIMM_31",
			  "SODIMM_23",
			  "SODIMM_29",
			  "SODIMM_71",
			  "SODIMM_73",
			  "SODIMM_92",
			  "SODIMM_81",
			  "SODIMM_131",
			  "SODIMM_129";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_168",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_184",
			  "SODIMM_186",
			  "HDMI_15",
			  "HDMI_16",
			  "SODIMM_178",
			  "SODIMM_188",
			  "SODIMM_56",
			  "SODIMM_44",
			  "SODIMM_68",
			  "SODIMM_82",
			  "SODIMM_24",
			  "SODIMM_76",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74";
};

&gpio5 {
	gpio-line-names = "SODIMM_95",
			  "",
			  "SODIMM_86",
			  "",
			  "SODIMM_65",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_57",
			  "SODIMM_61",
			  "SODIMM_136",
			  "SODIMM_138",
			  "SODIMM_140",
			  "SODIMM_142",
			  "SODIMM_144",
			  "SODIMM_146",
			  "SODIMM_172",
			  "SODIMM_170",
			  "SODIMM_149",
			  "SODIMM_151",
			  "SODIMM_153",
			  "SODIMM_155",
			  "SODIMM_157",
			  "SODIMM_159",
			  "SODIMM_161",
			  "SODIMM_163",
			  "SODIMM_33",
			  "SODIMM_35",
			  "SODIMM_165",
			  "SODIMM_167";
};

&gpio6 {
	gpio-line-names = "SODIMM_169",
			  "SODIMM_171",
			  "SODIMM_173",
			  "SODIMM_175",
			  "SODIMM_177",
			  "SODIMM_179",
			  "SODIMM_85",
			  "SODIMM_166",
			  "SODIMM_160",
			  "SODIMM_162",
			  "SODIMM_158",
			  "SODIMM_164",
			  "",
			  "",
			  "SODIMM_156",
			  "SODIMM_75",
			  "SODIMM_154",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_152";
};

&gpio7 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_19",
			  "SODIMM_21",
			  "",
			  "SODIMM_137";
};

&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_ddc>;
	status = "disabled";
};

/*
 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 * touch screen controller
 */
&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pmic@8 {
		compatible = "fsl,pfuze100";
		fsl,pmic-stby-poweroff;
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1875000>;
				regulator-min-microvolt = <300000>;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1875000>;
				regulator-min-microvolt = <300000>;
				regulator-ramp-delay = <6250>;
			};

			sw3a_reg: sw3a {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1975000>;
				regulator-min-microvolt = <400000>;
			};

			swbst_reg: swbst {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <5150000>;
				regulator-min-microvolt = <5000000>;
			};

			snvs_reg: vsnvs {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3000000>;
				regulator-min-microvolt = <1000000>;
			};

			vref_reg: vrefddr {
				regulator-always-on;
				regulator-boot-on;
			};

			/* vgen1: unused */

			vgen2_reg: vgen2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1550000>;
				regulator-min-microvolt = <800000>;
			};

			/*
			 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
			 * the i.MX 6 NVCC_SD1.
			 */
			vgen3_reg: vgen3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
			};

			vgen4_reg: vgen4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
			};

			vgen5_reg: vgen5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
			};

			vgen6_reg: vgen6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
			};
		};
	};

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		clocks = <&clks IMX6QDL_CLK_CKO>;
		lrclk-strength = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sgtl5000>;
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		VDDA-supply = <&reg_module_3v3_audio>;
		VDDIO-supply = <&reg_module_3v3>;
		VDDD-supply = <&vgen4_reg>;
	};

	/* STMPE811 touch screen controller */
	stmpe811@41 {
		compatible = "st,stmpe811";
		blocks = <0x5>;
		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
		interrupt-parent = <&gpio6>;
		interrupt-controller;
		id = <0>;
		irq-trigger = <0x1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_touch_int>;
		reg = <0x41>;
		/* 3.25 MHz ADC clock speed */
		st,adc-freq = <1>;
		/* 12-bit ADC */
		st,mod-12b = <1>;
		/* internal ADC reference */
		st,ref-sel = <0>;
		/* ADC converstion time: 80 clocks */
		st,sample-time = <4>;

		stmpe_ts: stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			/* 8 sample average control */
			st,ave-ctrl = <3>;
			/* 7 length fractional part in z */
			st,fraction-z = <7>;
			/*
			 * 50 mA typical 80 mA max touchscreen drivers
			 * current limit value
			 */
			st,i-drive = <1>;
			/* 1 ms panel driver settling time */
			st,settling = <3>;
			/* 5 ms touch detect interrupt delay */
			st,touch-det-delay = <5>;
			status = "disabled";
		};

		stmpe_adc: stmpe_adc {
			compatible = "st,stmpe-adc";
			/* forbid to use ADC channels 3-0 (touch) */
			st,norequest-mask = <0x0F>;
		};
	};
};

/*
 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 */
&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "disabled";

	atmel_mxt_ts: touchscreen@4a {
		compatible = "atmel,maxtouch";
		interrupt-parent = <&gpio2>;
		interrupts = <24 IRQ_TYPE_EDGE_FALLING>;	/* SODIMM 107 */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_atmel_conn>;
		reg = <0x4a>;
		reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;	/* SODIMM 106 */
		status = "disabled";
	};
};

&ipu1_di0_disp0 {
	remote-endpoint = <&lcd_display_in>;
};

/* Colibri PWM<B> */
&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "disabled";
};

/* Colibri PWM<D> */
&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "disabled";
};

/* Colibri PWM<A> */
&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
};

/* Colibri PWM<C> */
&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "disabled";
};

/* Optional S/PDIF out on SODIMM 137 */
&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "disabled";
};

&ssi1 {
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
	uart-has-rtscts;
	status = "disabled";
};

/* Colibri UART_B */
&uart2 {
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_dte>;
	uart-has-rtscts;
	status = "disabled";
};

/* Colibri UART_C */
&uart3 {
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_dte>;
	status = "disabled";
};

&usbotg {
	disable-over-current;
	dr_mode = "peripheral";
	status = "disabled";
};

/* Colibri MMC */
&usdhc1 {
	cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
	bus-width = <4>;
	no-1-8-v;
	disable-wp;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
	pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>;
	vmmc-supply = <&reg_module_3v3>;
	vqmmc-supply = <&vgen3_reg>;
	status = "disabled";
};

/* eMMC */
&usdhc3 {
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	vqmmc-supply = <&reg_module_3v3>;
	status = "okay";
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
		     &pinctrl_weim_cs1   &pinctrl_weim_cs2
		     &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
	#address-cells = <2>;
	#size-cells = <1>;
	status = "disabled";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbh_oc_1>;

	/* Atmel MXT touchsceen + Capacitive Touch Adapter */
	/* NOTE: This pin group conflicts with pin groups
	 * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously.
	 */
	pinctrl_atmel_adap: atmeladaptergrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_9__GPIO1_IO09   0xb0b1  /* SODIMM  28 */
			MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1  /* SODIMM  30 */
		>;
	};

	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
	/* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and
	 * pinctrl_weim_cs2. Don't use them simultaneously.
	 */
	pinctrl_atmel_conn: atmelconnectorgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0xb0b1  /* SODIMM_107 */
			MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1  /* SODIMM_106 */
		>;
	};

	pinctrl_audmux: audmuxgrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__AUD5_TXC	0x130b0
			MX6QDL_PAD_KEY_ROW0__AUD5_TXD	0x130b0
			MX6QDL_PAD_KEY_COL1__AUD5_TXFS	0x130b0
			MX6QDL_PAD_KEY_ROW1__AUD5_RXD	0x130b0
		>;
	};

	pinctrl_cam_mclk: cammclkgrp {
		fsl,pins = <
			/* Parallel Camera CAM sys_mclk */
			MX6QDL_PAD_NANDF_CS2__CCM_CLKO2	0x00b0
		>;
	};

	/* CSI pins used as GPIOs */
	pinctrl_csi_gpio_1: csigpio1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D18__GPIO3_IO18   0x1b0b0
			MX6QDL_PAD_EIM_A19__GPIO2_IO19   0x1b0b0
			MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x130b0
			MX6QDL_PAD_EIM_A23__GPIO6_IO06   0x1b0b0
			MX6QDL_PAD_EIM_A20__GPIO2_IO18   0x1b0b0
			MX6QDL_PAD_EIM_A17__GPIO2_IO21   0x1b0b0
			MX6QDL_PAD_EIM_A18__GPIO2_IO20   0x1b0b0
			MX6QDL_PAD_EIM_EB3__GPIO2_IO31   0x1b0b0
			MX6QDL_PAD_EIM_D17__GPIO3_IO17   0x1b0b0
			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
			MX6QDL_PAD_SD2_CMD__GPIO1_IO11   0x1b0b0
			MX6QDL_PAD_SD2_DAT0__GPIO1_IO15  0x1b0b0
		>;
	};

	pinctrl_csi_gpio_2: csigpio2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_A24__GPIO5_IO04   0x1b0b0
		>;
	};

	pinctrl_ecspi4: ecspi4grp {
		fsl,pins = <
			/* SPI CS */
			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x000b1
			MX6QDL_PAD_EIM_D22__ECSPI4_MISO	0x100b1
			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI	0x100b1
			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	((1<<30) | 0x1b0b0)
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
		>;
	};

	pinctrl_gpio_1: gpio1grp {
		fsl,pins = <
			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20     0x1b0b0
			MX6QDL_PAD_EIM_D27__GPIO3_IO27      0x1b0b0
			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
			MX6QDL_PAD_NANDF_D3__GPIO2_IO03     0x1b0b0
			MX6QDL_PAD_NANDF_D4__GPIO2_IO04     0x1b0b0
			MX6QDL_PAD_NANDF_D6__GPIO2_IO06     0x1b0b0
			MX6QDL_PAD_SD4_DAT0__GPIO2_IO08     0x1b0b0
			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11     0x1b0b0
		>;
	};
	pinctrl_gpio_2: gpio2grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_7__GPIO1_IO07       0x1b0b0
			MX6QDL_PAD_GPIO_8__GPIO1_IO08       0x1b0b0
		>;
	};

	pinctrl_gpio_bl_on: gpioblongrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x1b0b0
		>;
	};

	pinctrl_gpio_keys: gpiokeysgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x130b0
		>;
	};

	pinctrl_hdmi_ddc: hdmiddcgrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
			MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
			MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
			MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
			MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
		>;
	};

	pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
		fsl,pins = <
			MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12	0xb0b1
			MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13	0xb0b1
			MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14	0xb0b1
			MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15	0xb0b1
			MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16	0xb0b1
			MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17	0xb0b1
			MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18	0xb0b1
			MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19	0xb0b1
			MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK	0xb0b1
			MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC	0xb0b1
			MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC	0xb0b1
			/* Disable PWM pins on camera interface */
			MX6QDL_PAD_GPIO_1__GPIO1_IO01		0x40
			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x40
		>;
	};

	pinctrl_ipu1_lcdif: ipu1lcdifgrp {
		fsl,pins = <
			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0xa1
			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0xa1
			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0xa1
			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0xa1
			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0xa1
			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0xa1
			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0xa1
			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0xa1
			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0xa1
			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0xa1
			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0xa1
			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0xa1
			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0xa1
			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0xa1
			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0xa1
			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0xa1
			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0xa1
			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0xa1
			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0xa1
			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0xa1
			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0xa1
			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0xa1
		>;
	};

	pinctrl_lvds_transceiver: lvdstxgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM  95 */
			MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x0b030 /* SODIMM  55 */
			MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x03030 /* SODIMM  63 */
			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM  99 */
		>;
	};

	pinctrl_mic_gnd: micgndgrp {
		fsl,pins = <
			/* Controls Mic GND, PU or '1' pull Mic GND to GND */
			MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
		>;
	};

	pinctrl_mmc_cd: mmccdgrp {
		fsl,pins = <
			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x1b0b1
		>;
	};

	pinctrl_mmc_cd_sleep: mmccdslpgrp {
		fsl,pins = <
			MX6QDL_PAD_NANDF_D5__GPIO2_IO05	0x0
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_9__PWM1_OUT	0x1b0b1
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_A21__GPIO2_IO17	0x00040
			MX6QDL_PAD_GPIO_1__PWM2_OUT	0x1b0b1
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_A22__GPIO2_IO16	0x00040
			MX6QDL_PAD_SD4_DAT1__PWM3_OUT	0x1b0b1
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_DAT2__PWM4_OUT	0x1b0b1
		>;
	};

	pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
		fsl,pins = <
			/* USBH_EN */
			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x0f058
		>;
	};

	pinctrl_sgtl5000: sgtl5000grp {
		fsl,pins = <
			/* SGTL5000 sys_mclk */
			MX6QDL_PAD_GPIO_0__CCM_CLKO1	0x000b0
		>;
	};

	pinctrl_spdif: spdifgrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
		>;
	};

	pinctrl_touch_int: gpiotouchintgrp {
		fsl,pins = <
			/* STMPE811 interrupt */
			MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
		>;
	};

	pinctrl_uart1_dce: uart1dcegrp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
		>;
	};

	/* DTE mode */
	pinctrl_uart1_dte: uart1dtegrp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
			MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
			MX6QDL_PAD_EIM_D19__UART1_RTS_B	0x1b0b1
			MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
		>;
	};

	/* Additional DTR, DSR, DCD */
	pinctrl_uart1_ctrl: uart1ctrlgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
			MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
			MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
		>;
	};

	pinctrl_uart2_dte: uart2dtegrp {
		fsl,pins = <
			MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA	0x1b0b1
			MX6QDL_PAD_SD4_DAT5__UART2_CTS_B	0x1b0b1
			MX6QDL_PAD_SD4_DAT6__UART2_RTS_B	0x1b0b1
			MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_uart3_dte: uart3dtegrp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CLK__UART3_TX_DATA	0x1b0b1
			MX6QDL_PAD_SD4_CMD__UART3_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_usbc_det: usbcdetgrp {
		fsl,pins = <
			/* USBC_DET */
			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
			/* USBC_DET_OVERWRITE */
			MX6QDL_PAD_RGMII_RXC__GPIO6_IO30	0x0f058
			/* USBC_DET_EN */
			MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26	0x0f058
		>;
	};

	pinctrl_usbc_id_1: usbcid1grp {
		fsl,pins = <
			/* USBC_ID */
			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
		>;
	};

	pinctrl_usbh_oc_1: usbhoc1grp {
		fsl,pins = <
			/* USBH_OC */
			MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17071
			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10071
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17071
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17071
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17071
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17071
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x170b1
			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x100b1
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x170f1
			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x100f1
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
		>;
	};

	/* avoid backfeeding with removed card power */
	pinctrl_usdhc1_sleep: usdhc1sleepgrp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x3000
			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x3000
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x3000
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x3000
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x3000
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x3000
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
			/* eMMC reset */
			MX6QDL_PAD_SD3_RST__SD3_RESET	0x17059
		>;
	};

	pinctrl_weim_cs0: weimcs0grp {
		fsl,pins = <
			/* nEXT_CS0 */
			MX6QDL_PAD_EIM_CS0__EIM_CS0_B	0xb0b1
		>;
	};

	pinctrl_weim_cs1: weimcs1grp {
		fsl,pins = <
			/* nEXT_CS1 */
			MX6QDL_PAD_EIM_CS1__EIM_CS1_B	0xb0b1
		>;
	};

	pinctrl_weim_cs2: weimcs2grp {
		fsl,pins = <
			/* nEXT_CS2 */
			MX6QDL_PAD_SD2_DAT1__EIM_CS2_B	0xb0b1
		>;
	};

	/* ADDRESS[16:18] [25] used as GPIO */
	pinctrl_weim_gpio_1: weimgpio1grp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x1b0b0
			MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x1b0b0
			MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x1b0b0
			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x1b0b0
			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x1b0b0
			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
		>;
	};

	/* ADDRESS[19:24] used as GPIO */
	pinctrl_weim_gpio_2: weimgpio2grp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12	0x1b0b0
			MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13	0x1b0b0
			MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
			MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x1b0b0
			MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16	0x1b0b0
			MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17	0x1b0b0
			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
		>;
	};

	/* DATA[16:31] used as GPIO */
	pinctrl_weim_gpio_3: weimgpio3grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19	0x1b0b0
			MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18	0x1b0b0
			MX6QDL_PAD_EIM_LBA__GPIO2_IO27		0x1b0b0
			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0x1b0b0
			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0
			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x1b0b0
			MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
			MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x1b0b0
			MX6QDL_PAD_NANDF_CS0__GPIO6_IO11	0x1b0b0
			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x1b0b0
			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x1b0b0
			MX6QDL_PAD_NANDF_CLE__GPIO6_IO07	0x1b0b0
			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	0x1b0b0
			MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x1b0b0
		>;
	};

	/* DQM[0:3] used as GPIO */
	pinctrl_weim_gpio_4: weimgpio4grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0x1b0b0
			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x1b0b0
			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
			MX6QDL_PAD_SD2_DAT2__GPIO1_IO13		0x1b0b0
		>;
	};

	/* RDY used as GPIO */
	pinctrl_weim_gpio_5: weimgpio5grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x1b0b0
		>;
	};

	/* ADDRESS[16] DATA[30] used as GPIO */
	pinctrl_weim_gpio_6: weimgpio6grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0
			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
		>;
	};

	pinctrl_weim_npwe: weimnpwegrp {
		fsl,pins = <
			MX6QDL_PAD_RGMII_TD2__GPIO6_IO22	0x130b0
			MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x0040
		>;
	};

	pinctrl_weim_sram: weimsramgrp {
		fsl,pins = <
			/* Data */
			MX6QDL_PAD_CSI0_DAT4__EIM_DATA02	0x1b0b0
			MX6QDL_PAD_CSI0_DAT5__EIM_DATA03	0x1b0b0
			MX6QDL_PAD_CSI0_DAT6__EIM_DATA04	0x1b0b0
			MX6QDL_PAD_CSI0_DAT7__EIM_DATA05	0x1b0b0
			MX6QDL_PAD_CSI0_DAT8__EIM_DATA06	0x1b0b0
			MX6QDL_PAD_CSI0_DAT9__EIM_DATA07	0x1b0b0
			MX6QDL_PAD_CSI0_DAT12__EIM_DATA08	0x1b0b0
			MX6QDL_PAD_CSI0_DAT13__EIM_DATA09	0x1b0b0
			MX6QDL_PAD_CSI0_DAT14__EIM_DATA10	0x1b0b0
			MX6QDL_PAD_CSI0_DAT15__EIM_DATA11	0x1b0b0
			MX6QDL_PAD_CSI0_DAT16__EIM_DATA12	0x1b0b0
			MX6QDL_PAD_CSI0_DAT17__EIM_DATA13	0x1b0b0
			MX6QDL_PAD_CSI0_DAT18__EIM_DATA14	0x1b0b0
			MX6QDL_PAD_CSI0_DAT19__EIM_DATA15	0x1b0b0
			MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00	0x1b0b0
			MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01	0x1b0b0
			/* Address */
			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
			/* Ctrl */
			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
		>;
	};

	pinctrl_weim_rdnwr: weimrdnwrgrp {
		fsl,pins = <
			MX6QDL_PAD_RGMII_TD3__GPIO6_IO23	0x130b0
			MX6QDL_PAD_SD2_CLK__GPIO1_IO10		0x0040
		>;
	};
};