u-boot/drivers/ddr/imx/imx8ulp/Kconfig

menu "i.MX8ULP DDR controllers"
	depends on ARCH_IMX8ULP

config IMX8ULP_DRAM
	bool "imx8m dram"

config IMX8ULP_DRAM_PHY_PLL_BYPASS
	bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
	depends on IMX8ULP_DRAM

endmenu
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com> 2021-08-07 08:01:11 +00:00			`menu "i.MX8ULP DDR controllers"`
			`depends on ARCH_IMX8ULP`

			`config IMX8ULP_DRAM`
			`bool "imx8m dram"`

			`config IMX8ULP_DRAM_PHY_PLL_BYPASS`
			`bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "`
			`depends on IMX8ULP_DRAM`

			`endmenu`