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u-boot/include/virtex2.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
Initial revision
2002-11-03 00:24:07 +00:00
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
*/
#ifndef _VIRTEX2_H_
#define _VIRTEX2_H_
#include <xilinx.h>
/*
fpga: virtex2: Add slave serial programming support This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-06-18 15:47:16 +00:00
* Slave SelectMap or Serial Implementation function table.
Initial revision
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*/
typedef struct {
fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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xilinx_pre_fn pre;
xilinx_pgm_fn pgm;
xilinx_init_fn init;
xilinx_err_fn err;
xilinx_done_fn done;
xilinx_clk_fn clk;
xilinx_cs_fn cs;
xilinx_wr_fn wr;
xilinx_rdata_fn rdata;
xilinx_wdata_fn wdata;
fpga: virtex2: Add slave serial programming support This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-06-18 15:47:16 +00:00
xilinx_bwr_fn wbulkdata;
fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-03-13 11:58:20 +00:00
xilinx_busy_fn busy;
xilinx_abort_fn abort;
xilinx_post_fn post;
fpga: virtex2: Add slave serial programming support This adds support for slave serial programming, in addition to the previously supported slave SelectMAP mode. There are two ways that this can be used: -Using the clk and wdata callbacks in order to write image data one bit at a time using pure bit-banging. This works, but is rather painfully slow with typical image sizes. -By specifying the wbulkdata callback instead, the image loading process can be offloaded to SPI hardware. In this mode the clk and wdata callbacks do not need to be specified. This allows the image to be loaded much faster, taking only a few seconds with even relatively large images. Slave serial programming has been tested on the Kintex-7 series of FPGAs. Signed-off-by: Robert Hancock <hancock@sedsystems.ca> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-06-18 15:47:16 +00:00
} xilinx_virtex2_slave_fns;
Initial revision
2002-11-03 00:24:07 +00:00
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-16 08:48:08 +00:00
#if defined(CONFIG_FPGA_VIRTEX2)
extern struct xilinx_fpga_op virtex2_op;
# define FPGA_VIRTEX2_OPS &virtex2_op
#else
# define FPGA_VIRTEX2_OPS NULL
#endif
Initial revision
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/* Device Image Sizes (in bytes)
*********************************************************************/
fpga: xilinx: virtex2: Fix macro indentation No functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-16 08:47:43 +00:00
#define XILINX_XC2V40_SIZE (338208 / 8)
#define XILINX_XC2V80_SIZE (597408 / 8)
#define XILINX_XC2V250_SIZE (1591584 / 8)
#define XILINX_XC2V500_SIZE (2557857 / 8)
Initial revision
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#define XILINX_XC2V1000_SIZE (3749408 / 8)
#define XILINX_XC2V1500_SIZE (5166240 / 8)
#define XILINX_XC2V2000_SIZE (6808352 / 8)
#define XILINX_XC2V3000_SIZE (9589408 / 8)
#define XILINX_XC2V4000_SIZE (14220192 / 8)
#define XILINX_XC2V6000_SIZE (19752096 / 8)
#define XILINX_XC2V8000_SIZE (26185120 / 8)
#define XILINX_XC2V10000_SIZE (33519264 / 8)
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
2002-11-03 00:24:07 +00:00
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-16 08:48:08 +00:00
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
2002-11-03 00:24:07 +00:00
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
2002-11-03 00:24:07 +00:00
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-16 08:48:08 +00:00
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
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#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
fpga: xilinx: virtex2: Setup NULL fpga_op without driver Set fpga operations to NULL for cases where FPGA is setup in board file but driver is not added Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-07-16 08:48:08 +00:00
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
FPGA_VIRTEX2_OPS }
Initial revision
2002-11-03 00:24:07 +00:00
#endif /* _VIRTEX2_H_ */
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