2021-01-27 11:00:00 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device tree fragment for RCW SCH-30841 card
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*
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2021-09-17 11:27:13 +00:00
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* Copyright 2019-2021 NXP
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2021-01-27 11:00:00 +00:00
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*/
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/*
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* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
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* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
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* together on a single lane or mapped 1:1 to serdes lanes.
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net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x"
After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/
which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/
and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/
it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.
So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.
As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.
This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.
Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.
NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-18 12:32:35 +00:00
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* It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
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2021-01-27 11:00:00 +00:00
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* PHY addresses are 0x00 - 0x03.
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* On the card the first port is the bottom port (closest to PEX connector).
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*/
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phy@00 {
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reg = <0x00>;
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mdi-reversal = <1>;
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smb-addr = <0x25>;
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};
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phy@01 {
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reg = <0x01>;
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mdi-reversal = <1>;
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smb-addr = <0x26>;
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};
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phy@02 {
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reg = <0x02>;
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mdi-reversal = <1>;
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smb-addr = <0x27>;
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};
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phy@03 {
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reg = <0x03>;
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mdi-reversal = <1>;
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smb-addr = <0x28>;
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};
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