2018-08-27 10:27:09 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
|
|
|
/*
|
2020-01-10 19:35:20 +00:00
|
|
|
* AM6: SoC specific initialization
|
2018-08-27 10:27:09 +00:00
|
|
|
*
|
|
|
|
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
|
|
|
|
* Lokesh Vutla <lokeshvutla@ti.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2018-08-27 10:27:11 +00:00
|
|
|
#include <asm/io.h>
|
2018-08-27 10:27:09 +00:00
|
|
|
#include <spl.h>
|
2018-08-27 10:27:11 +00:00
|
|
|
#include <asm/arch/hardware.h>
|
2019-06-04 22:55:50 +00:00
|
|
|
#include <asm/arch/sysfw-loader.h>
|
2019-06-04 23:08:26 +00:00
|
|
|
#include <asm/arch/sys_proto.h>
|
2018-11-02 14:21:03 +00:00
|
|
|
#include "common.h"
|
2018-11-02 14:21:06 +00:00
|
|
|
#include <dm.h>
|
2019-06-04 22:55:50 +00:00
|
|
|
#include <dm/uclass-internal.h>
|
|
|
|
#include <dm/pinctrl.h>
|
2019-06-07 13:54:42 +00:00
|
|
|
#include <linux/soc/ti/ti_sci_protocol.h>
|
2020-02-26 08:14:36 +00:00
|
|
|
#include <mmc.h>
|
2018-08-27 10:27:09 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
2020-01-10 19:35:21 +00:00
|
|
|
#ifdef CONFIG_K3_LOAD_SYSFW
|
|
|
|
#ifdef CONFIG_TI_SECURE_DEVICE
|
|
|
|
struct fwl_data main_cbass_fwls[] = {
|
|
|
|
{ "MMCSD1_CFG", 2057, 1 },
|
|
|
|
{ "MMCSD0_CFG", 2058, 1 },
|
|
|
|
{ "USB3SS0_SLV0", 2176, 2 },
|
|
|
|
{ "PCIE0_SLV", 2336, 8 },
|
|
|
|
{ "PCIE1_SLV", 2337, 8 },
|
|
|
|
{ "PCIE0_CFG", 2688, 1 },
|
|
|
|
{ "PCIE1_CFG", 2689, 1 },
|
|
|
|
}, mcu_cbass_fwls[] = {
|
|
|
|
{ "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
|
|
|
|
{ "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
|
|
|
|
{ "MCU_FSS0_S1", 1033, 8 },
|
|
|
|
{ "MCU_FSS0_S0", 1036, 8 },
|
|
|
|
{ "MCU_CPSW0", 1220, 1 },
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
2018-08-27 10:27:12 +00:00
|
|
|
static void mmr_unlock(u32 base, u32 partition)
|
|
|
|
{
|
|
|
|
/* Translate the base address */
|
|
|
|
phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
|
|
|
|
|
|
|
|
/* Unlock the requested partition if locked using two-step sequence */
|
|
|
|
writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
|
|
|
|
writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ctrl_mmr_unlock(void)
|
|
|
|
{
|
|
|
|
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
|
|
|
|
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
|
|
|
|
|
|
|
|
/* Unlock all MCU_CTRL_MMR0 module registers */
|
|
|
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
|
|
|
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
|
|
|
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
|
|
|
|
mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
|
|
|
|
|
|
|
|
/* Unlock all CTRL_MMR0 module registers */
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 0);
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 1);
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 2);
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 3);
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 6);
|
|
|
|
mmr_unlock(CTRL_MMR0_BASE, 7);
|
|
|
|
}
|
|
|
|
|
2019-04-12 16:54:42 +00:00
|
|
|
/*
|
|
|
|
* This uninitialized global variable would normal end up in the .bss section,
|
|
|
|
* but the .bss is cleared between writing and reading this variable, so move
|
|
|
|
* it to the .data section.
|
|
|
|
*/
|
|
|
|
u32 bootindex __attribute__((section(".data")));
|
|
|
|
|
2018-08-27 10:27:11 +00:00
|
|
|
static void store_boot_index_from_rom(void)
|
|
|
|
{
|
2019-04-12 16:54:42 +00:00
|
|
|
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
2018-08-27 10:27:11 +00:00
|
|
|
}
|
|
|
|
|
2020-02-26 08:14:36 +00:00
|
|
|
#if defined(CONFIG_K3_LOAD_SYSFW)
|
|
|
|
void k3_mmc_stop_clock(void)
|
|
|
|
{
|
|
|
|
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
|
|
|
struct mmc *mmc = find_mmc_device(0);
|
|
|
|
|
|
|
|
if (!mmc)
|
|
|
|
return;
|
|
|
|
|
|
|
|
mmc->saved_clock = mmc->clock;
|
|
|
|
mmc_set_clock(mmc, 0, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void k3_mmc_restart_clock(void)
|
|
|
|
{
|
|
|
|
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
|
|
|
struct mmc *mmc = find_mmc_device(0);
|
|
|
|
|
|
|
|
if (!mmc)
|
|
|
|
return;
|
|
|
|
|
|
|
|
mmc_set_clock(mmc, mmc->saved_clock, false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-08-27 10:27:09 +00:00
|
|
|
void board_init_f(ulong dummy)
|
|
|
|
{
|
2019-06-04 22:55:50 +00:00
|
|
|
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
|
2018-11-02 14:21:06 +00:00
|
|
|
struct udevice *dev;
|
|
|
|
int ret;
|
|
|
|
#endif
|
2018-08-27 10:27:11 +00:00
|
|
|
/*
|
|
|
|
* Cannot delay this further as there is a chance that
|
|
|
|
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
|
|
|
*/
|
|
|
|
store_boot_index_from_rom();
|
|
|
|
|
2018-08-27 10:27:12 +00:00
|
|
|
/* Make all control module registers accessible */
|
|
|
|
ctrl_mmr_unlock();
|
|
|
|
|
2018-11-02 14:21:03 +00:00
|
|
|
#ifdef CONFIG_CPU_V7R
|
2019-12-31 10:19:55 +00:00
|
|
|
disable_linefill_optimization();
|
2018-11-02 14:21:03 +00:00
|
|
|
setup_k3_mpu_regions();
|
|
|
|
#endif
|
|
|
|
|
2018-08-27 10:27:09 +00:00
|
|
|
/* Init DM early in-order to invoke system controller */
|
|
|
|
spl_early_init();
|
|
|
|
|
2018-12-05 04:29:47 +00:00
|
|
|
#ifdef CONFIG_K3_EARLY_CONS
|
|
|
|
/*
|
|
|
|
* Allow establishing an early console as required for example when
|
|
|
|
* doing a UART-based boot. Note that this console may not "survive"
|
|
|
|
* through a SYSFW PM-init step and will need a re-init in some way
|
|
|
|
* due to changing module clock frequencies.
|
|
|
|
*/
|
|
|
|
early_console_init();
|
|
|
|
#endif
|
|
|
|
|
2019-06-04 22:55:50 +00:00
|
|
|
#ifdef CONFIG_K3_LOAD_SYSFW
|
|
|
|
/*
|
|
|
|
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
|
|
|
|
* regardless of the result of pinctrl. Do this without probing the
|
|
|
|
* device, but instead by searching the device that would request the
|
|
|
|
* given sequence number if probed. The UART will be used by the system
|
|
|
|
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
|
|
|
* to initialize its pin settings.
|
|
|
|
*/
|
|
|
|
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
|
|
|
|
if (!ret)
|
|
|
|
pinctrl_select_state(dev, "default");
|
|
|
|
|
|
|
|
/*
|
2020-03-10 11:20:58 +00:00
|
|
|
* Load, start up, and configure system controller firmware while
|
|
|
|
* also populating the SYSFW post-PM configuration callback hook.
|
2019-06-04 22:55:50 +00:00
|
|
|
*/
|
2020-02-26 08:14:36 +00:00
|
|
|
k3_sysfw_loader(k3_mmc_stop_clock, k3_mmc_restart_clock);
|
|
|
|
|
|
|
|
/* Prepare console output */
|
|
|
|
preloader_console_init();
|
2020-01-10 19:35:21 +00:00
|
|
|
|
|
|
|
/* Disable ROM configured firewalls right after loading sysfw */
|
|
|
|
#ifdef CONFIG_TI_SECURE_DEVICE
|
|
|
|
remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
|
|
|
|
remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
|
|
|
|
#endif
|
2019-06-04 22:55:50 +00:00
|
|
|
#else
|
2018-08-27 10:27:09 +00:00
|
|
|
/* Prepare console output */
|
|
|
|
preloader_console_init();
|
2019-06-04 22:55:50 +00:00
|
|
|
#endif
|
2018-11-02 14:21:06 +00:00
|
|
|
|
2020-03-10 11:20:58 +00:00
|
|
|
/* Output System Firmware version info */
|
|
|
|
k3_sysfw_print_ver();
|
|
|
|
|
2019-06-04 23:08:26 +00:00
|
|
|
/* Perform EEPROM-based board detection */
|
|
|
|
do_board_detect();
|
|
|
|
|
2019-10-24 09:30:52 +00:00
|
|
|
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
|
|
|
|
&dev);
|
|
|
|
if (ret)
|
|
|
|
printf("AVS init failed: %d\n", ret);
|
|
|
|
#endif
|
|
|
|
|
2018-11-02 14:21:06 +00:00
|
|
|
#ifdef CONFIG_K3_AM654_DDRSS
|
|
|
|
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
2019-03-11 20:15:43 +00:00
|
|
|
if (ret)
|
|
|
|
panic("DRAM init failed: %d\n", ret);
|
2018-11-02 14:21:06 +00:00
|
|
|
#endif
|
2018-08-27 10:27:09 +00:00
|
|
|
}
|
|
|
|
|
2020-04-15 09:33:30 +00:00
|
|
|
u32 spl_mmc_boot_mode(const u32 boot_device)
|
2018-10-03 15:03:23 +00:00
|
|
|
{
|
|
|
|
#if defined(CONFIG_SUPPORT_EMMC_BOOT)
|
|
|
|
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
|
|
|
|
|
|
|
u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
|
|
|
|
|
|
|
|
/* eMMC boot0 mode is only supported for primary boot */
|
|
|
|
if (bootindex == K3_PRIMARY_BOOTMODE &&
|
|
|
|
bootmode == BOOT_DEVICE_MMC1)
|
|
|
|
return MMCSD_MODE_EMMCBOOT;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* Everything else use filesystem if available */
|
2019-01-23 06:20:05 +00:00
|
|
|
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
|
2018-10-03 15:03:23 +00:00
|
|
|
return MMCSD_MODE_FS;
|
|
|
|
#else
|
|
|
|
return MMCSD_MODE_RAW;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2018-08-27 10:27:11 +00:00
|
|
|
static u32 __get_backup_bootmedia(u32 devstat)
|
2018-08-27 10:27:09 +00:00
|
|
|
{
|
2018-08-27 10:27:11 +00:00
|
|
|
u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
|
|
|
|
|
|
|
|
switch (bkup_boot) {
|
|
|
|
case BACKUP_BOOT_DEVICE_USB:
|
|
|
|
return BOOT_DEVICE_USB;
|
|
|
|
case BACKUP_BOOT_DEVICE_UART:
|
|
|
|
return BOOT_DEVICE_UART;
|
|
|
|
case BACKUP_BOOT_DEVICE_ETHERNET:
|
|
|
|
return BOOT_DEVICE_ETHERNET;
|
|
|
|
case BACKUP_BOOT_DEVICE_MMC2:
|
2018-10-03 15:03:22 +00:00
|
|
|
{
|
|
|
|
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
|
|
|
|
if (port == 0x0)
|
|
|
|
return BOOT_DEVICE_MMC1;
|
2018-08-27 10:27:11 +00:00
|
|
|
return BOOT_DEVICE_MMC2;
|
2018-10-03 15:03:22 +00:00
|
|
|
}
|
2018-08-27 10:27:11 +00:00
|
|
|
case BACKUP_BOOT_DEVICE_SPI:
|
|
|
|
return BOOT_DEVICE_SPI;
|
|
|
|
case BACKUP_BOOT_DEVICE_HYPERFLASH:
|
|
|
|
return BOOT_DEVICE_HYPERFLASH;
|
|
|
|
case BACKUP_BOOT_DEVICE_I2C:
|
|
|
|
return BOOT_DEVICE_I2C;
|
|
|
|
};
|
|
|
|
|
2018-08-27 10:27:09 +00:00
|
|
|
return BOOT_DEVICE_RAM;
|
|
|
|
}
|
2018-08-27 10:27:11 +00:00
|
|
|
|
|
|
|
static u32 __get_primary_bootmedia(u32 devstat)
|
|
|
|
{
|
2018-10-03 15:03:22 +00:00
|
|
|
u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
|
2018-08-27 10:27:11 +00:00
|
|
|
|
|
|
|
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
|
|
|
|
bootmode = BOOT_DEVICE_SPI;
|
|
|
|
|
2018-10-03 15:03:22 +00:00
|
|
|
if (bootmode == BOOT_DEVICE_MMC2) {
|
|
|
|
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
|
|
|
|
if (port == 0x0)
|
|
|
|
bootmode = BOOT_DEVICE_MMC1;
|
|
|
|
} else if (bootmode == BOOT_DEVICE_MMC1) {
|
|
|
|
u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
|
|
|
|
CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
|
|
|
|
if (port == 0x1)
|
|
|
|
bootmode = BOOT_DEVICE_MMC2;
|
|
|
|
}
|
|
|
|
|
2018-08-27 10:27:11 +00:00
|
|
|
return bootmode;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32 spl_boot_device(void)
|
|
|
|
{
|
|
|
|
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
|
|
|
|
|
|
|
if (bootindex == K3_PRIMARY_BOOTMODE)
|
|
|
|
return __get_primary_bootmedia(devstat);
|
|
|
|
else
|
|
|
|
return __get_backup_bootmedia(devstat);
|
|
|
|
}
|
2018-08-27 10:27:09 +00:00
|
|
|
#endif
|
|
|
|
|
2019-06-07 13:54:42 +00:00
|
|
|
#ifdef CONFIG_SYS_K3_SPL_ATF
|
|
|
|
|
|
|
|
#define AM6_DEV_MCU_RTI0 134
|
|
|
|
#define AM6_DEV_MCU_RTI1 135
|
|
|
|
#define AM6_DEV_MCU_ARMSS0_CPU0 159
|
|
|
|
#define AM6_DEV_MCU_ARMSS0_CPU1 245
|
|
|
|
|
|
|
|
void release_resources_for_core_shutdown(void)
|
|
|
|
{
|
2019-09-09 07:17:38 +00:00
|
|
|
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
|
|
|
|
struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
|
|
|
|
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
|
2019-06-07 13:54:42 +00:00
|
|
|
int ret;
|
|
|
|
u32 i;
|
|
|
|
|
|
|
|
const u32 put_device_ids[] = {
|
|
|
|
AM6_DEV_MCU_RTI0,
|
|
|
|
AM6_DEV_MCU_RTI1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Iterate through list of devices to put (shutdown) */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
|
|
|
|
u32 id = put_device_ids[i];
|
|
|
|
|
|
|
|
ret = dev_ops->put_device(ti_sci, id);
|
|
|
|
if (ret)
|
|
|
|
panic("Failed to put device %u (%d)\n", id, ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
const u32 put_core_ids[] = {
|
|
|
|
AM6_DEV_MCU_ARMSS0_CPU1,
|
|
|
|
AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Iterate through list of cores to put (shutdown) */
|
|
|
|
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
|
|
|
|
u32 id = put_core_ids[i];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Queue up the core shutdown request. Note that this call
|
|
|
|
* needs to be followed up by an actual invocation of an WFE
|
|
|
|
* or WFI CPU instruction.
|
|
|
|
*/
|
|
|
|
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
|
|
|
|
if (ret)
|
|
|
|
panic("Failed sending core %u shutdown message (%d)\n",
|
|
|
|
id, ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|