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u-boot/board/amcc/ocotea/init.S

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* Patch by Travis Sawyer, 01 Mar 2004: Ocotea: - Add IBM PPC440GX Ref Platform support (Ocotea) Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> Adapted to U-Boot and 440GX port 440gx_enet.c: - Add gracious handling of all Ethernet Pin Selections for 440GX - Add RGMII selection for Cicada CIS8201 Gigabit PHY ppc440.h: - Add needed bit definitions - Fix formatting * Patch by Carl Riechers, 1 Mar 2004: Add PPC440GX prbdv0 divider to fix memory clock calculation. * Patch by Stephan Linz, 27 Feb 2004 - avoid problems for targets without NFS download support
2004-03-14 00:07:33 +00:00
/*
Fix TLB setup for Ocotea board Patch by Stefan Roese, 30 Sep 2006
2006-10-04 05:12:49 +00:00
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
Coding Style cleanup: remove trailing white space Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-07 11:07:26 +00:00
* SPDX-License-Identifier: GPL-2.0+
Fix TLB setup for Ocotea board Patch by Stefan Roese, 30 Sep 2006
2006-10-04 05:12:49 +00:00
*/
* Patch by Travis Sawyer, 01 Mar 2004: Ocotea: - Add IBM PPC440GX Ref Platform support (Ocotea) Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> Adapted to U-Boot and 440GX port 440gx_enet.c: - Add gracious handling of all Ethernet Pin Selections for 440GX - Add RGMII selection for Cicada CIS8201 Gigabit PHY ppc440.h: - Add needed bit definitions - Fix formatting * Patch by Carl Riechers, 1 Mar 2004: Add PPC440GX prbdv0 divider to fix memory clock calculation. * Patch by Stephan Linz, 27 Feb 2004 - avoid problems for targets without NFS download support
2004-03-14 00:07:33 +00:00
#include <ppc_asm.tmpl>
#include <config.h>
Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>" The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 03:28:07 +00:00
#include <asm/mmu.h>
ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-20 14:05:31 +00:00
#include <asm/ppc4xx.h>
* Patch by Travis Sawyer, 01 Mar 2004: Ocotea: - Add IBM PPC440GX Ref Platform support (Ocotea) Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> Adapted to U-Boot and 440GX port 440gx_enet.c: - Add gracious handling of all Ethernet Pin Selections for 440GX - Add RGMII selection for Cicada CIS8201 Gigabit PHY ppc440.h: - Add needed bit definitions - Fix formatting * Patch by Carl Riechers, 1 Mar 2004: Add PPC440GX prbdv0 divider to fix memory clock calculation. * Patch by Stephan Linz, 27 Feb 2004 - avoid problems for targets without NFS download support
2004-03-14 00:07:33 +00:00
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
[PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 15:43:00 +00:00
.section .bootpg,"ax"
.globl tlbtab
* Patch by Travis Sawyer, 01 Mar 2004: Ocotea: - Add IBM PPC440GX Ref Platform support (Ocotea) Original code by Paul Reynolds <PaulReynolds@lhsolutions.com> Adapted to U-Boot and 440GX port 440gx_enet.c: - Add gracious handling of all Ethernet Pin Selections for 440GX - Add RGMII selection for Cicada CIS8201 Gigabit PHY ppc440.h: - Add needed bit definitions - Fix formatting * Patch by Carl Riechers, 1 Mar 2004: Add PPC440GX prbdv0 divider to fix memory clock calculation. * Patch by Stephan Linz, 27 Feb 2004 - avoid problems for targets without NFS download support
2004-03-14 00:07:33 +00:00
tlbtab:
[PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 15:43:00 +00:00
tlbtab_start
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
[PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 15:43:00 +00:00
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
2010-04-14 11:57:18 +00:00
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
[PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 15:43:00 +00:00
tlbtab_end
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